Hawk Instruction Set Summary and Index

Note: Parenthetic notes indicate: (nz) must not be zero; (x) if zero, discard result; (pc) if zero, use pc; and (16) if zero, use the value 16.

C.1. Instruction Set Summary

Instructions are listed in reverse numeric order, with opcodes given in binary. This is the same order as the instructions appear in in the body of the manual. Each group of instructions corresponds to a chapter, and the synonyms listed for each group are alternate instruction names for special-case uses of instructions in that group.

C.1.1. Short Memory Reference Format (See Chapter 2)

07	06	05	04	03	02	01	00	15	14	13	12	11	10	09	08

1 1 1 1				dst (nz)				1 1 1 1				x (pc)				MOVE	dst,x	r[dst] = ea
1 1 1 1				dst (x)				1 1 1 0				x (pc)				MOVECC	dst,x	r[dst] = ea
1 1 1 1				dst (pc)				1 1 0 1				x (pc)				LOADS	dst,x	r[dst] = M[ea]
1 1 1 1				dst (x)				1 1 0 0				x (pc)				LOADSCC	dst,x	r[dst] = M[ea]
1 1 1 1				dst (x)				1 0 1 1				x (pc)				JSRS	dst,x	r[dst] = pc; pc = ea
1 1 1 1				srcx (0)				1 0 1 0				x (nz)				STORES	srcx,x	m[ea] = r[srcx]
1 1 1 1				dst (x)				1 0 0 1				x (nz)				LOADL	dst,x	r[dst] = m[ea]
1 1 1 1				srcx (0)				1 0 0 0				x (nz)				STOREC	srcx,x	if ok, m[ea] = r[srcx]

Synonyms

07	06	05	04	03	02	01	00	15	14	13	12	11	10	09	08

1 1 1 1				0 0 0 0				1 1 1 0				x (pc)				TESTR	x
1 1 1 1				0 0 0 0				1 1 0 0				x (pc)				TESTS	x
1 1 1 1				0 0 0 0				1 0 1 1				x (pc)				JUMPS	dst,x	pc = ea
1 1 1 1 0 0 0 0								1 1 1 0				x (pc)				BITTST	x,31	b = 31

C.1.2. Memory Reference Format (See Chapter 3)

07	06	05	04	03	02	01	00	15	14	13	12	11	10	09	08

1 1 1 1				dst (nz)				0 1 1 1				x (pc)				LEA	dst,x,disp	r[dst] = ea
1 1 1 1				dst (x)				0 1 1 0				x (pc)				LEACC	dst,x,disp	r[dst] = ea
1 1 1 1				dst (pc)				0 1 0 1				x (pc)				LOAD	dst,x,disp	r[dst] = m[ea]
1 1 1 1				dst (x)				0 1 0 0				x (pc)				LOADCC	dst,x,disp	r[dst] = m[ea]
1 1 1 1				dst (x)				0 0 1 1				x (pc)				JSR	dst,x,disp	r[dst] = pc; pc = ea
1 1 1 1				srcx (0)				0 0 1 0				x (pc)				STORE	srcx,x,disp	m[ea] = r[srcx]
1 1 1 1								0 0 0 1								—
1 1 1 1								0 0 0 0								—

Synonyms

07	06	05	04	03	02	01	00	15	14	13	12	11	10	09	08

1 1 1 1				dst (x)				0 1 1 0				x (pc)				ADDI	dst,x,disp	r[dst] = ea
1 1 1 1				0 0 0 0				0 1 1 0				x (pc)				CMPI	x,-disp
1 1 1 1				0 0 0 0				0 1 0 0				x (pc)				TEST	x,disp
1 1 1 1				0 0 0 0				0 0 1 1				x (pc)				JUMP	x,disp	pc = ea

C.1.3. Long Immediate Format (See Chapter 4)

07	06	05	04	03	02	01	00	15	14	13	12	11	10	09	08

1 1 1 0				dst (pc)				const:7:0								LIL	dst,const	r[dst] = sx(const)

C.1.4. Short Immediate Format (See Chapter 5)

07	06	05	04	03	02	01	00	15	14	13	12	11	10	09	08

1 1 0 1				dst (nz)				const								LIS	dst,const	r[dst] = sx(const)
1 1 0 0				dst (nz)				const								ORIS	dst,const	r[dst]=r[dst]<<8∨const

Synonyms

07	06	05	04	03	02	01	00	15	14	13	12	11	10	09	08

1 1 0 1				dst (nz)				0 0 0 0 0 0 0 0								CLR	dst	r[dst] = 0

C.1.5. Shift Format (See Chapter 6)

07	06	05	04	03	02	01	00	15	14	13	12	11	10	09	08

1 0 1 1				dst (x)				s1 (nz)				s2 (16)				MOVESL	dst,s1,s	r[dst] = r[s1]<<s
1 0 1 0				dst (nz)				s1 (0)				s2 (16)				ADDSL	dst,s1,s	r[dst]=r[dst]<<s + r[s1]
1 0 0 1				dst (x)				s1 (0)				s2 (16)				ADDSR	dst,s1,s	r[dst]=(r[dst]+r[s1])>>s
1 0 0 0				dst (x)				s1 (0)				s2 (16)				ADDSRU	dst,s1,s	r[dst]=(r[dst]+r[s1])>>>s

Synonyms

07	06	05	04	03	02	01	00	15	14	13	12	11	10	09	08

1 0 1 0				dst (nz)				0 0 0 0				s2 (16)				SL	dst,s	r[dst] = r[dst] << s
1 0 0 1				dst (x)				0 0 0 0				s2 (16)				SR	dst,s	r[dst] = r[dst] >> s
1 0 0 0				dst (x)				0 0 0 0				s2 (16)				SRU	dst,s	r[dst] = r[dst] >>> s
1 0 0 1 0 0 0 0								s1 (0)				s2 (16)				BITTST	dst,s-1	0 ≤ b ≤ 15: s = b + 1
1 0 1 1 0 0 0 0								s1 (nz)				s2 (16)				BITTST	s1,31-s	16 ≤ b ≤ 30: s = 31 - b

C.1.6. Byte and Halfword Format (See Chapter 7)

07	06	05	04	03	02	01	00	15	14	13	12	11	10	09	08

0 1 1 1				dst (nz)				s1 (0)				s2 (0)				STUFFB	dst,s1,s2	r[dst]:b+7:b = r[s1]
0 1 1 0				dst (nz)				s1 (0)				s2 (0)				STUFFH	dst,s1,s2	r[dst]:h+15:h = r[s1]
0 1 0 1				dst (x)				s1 (nz)				s2 (0)				EXTB	dst,s1,s2	r[dst] = r[s1]:b+7:b
0 1 0 0				dst (x)				s1 (nz)				s2 (0)				EXTH	dst,s1,s2	r[dst] = r[s1]:b+15:b

C.1.7. Add and Subtract Format (See Chapter 8)

07	06	05	04	03	02	01	00	15	14	13	12	11	10	09	08

0 0 1 1				dst (x)				s1 (nz)				s2 (nz)				ADD	dst,s1,s2	r[dst] = r[s1] + r[s2]
0 0 1 0				dst (x)				s1 (0)				s2 (nz)				SUB	dst,s1,s2	r[dst] = r[s1] – r[s2]

Synonyms

07	06	05	04	03	02	01	00	15	14	13	12	11	10	09	08

0 0 1 0				dst (x)				0 0 0 0				s2 (nz)				NEG	dst,s2	r[dst] = 0 – r[s2]
0 0 1 0				0 0 0 0				s1 (0)				s2 (nz)				CMP	s1,s2

C.1.8. Short Constant Format (See Chapter 9)

07	06	05	04	03	02	01	00	15	14	13	12	11	10	09	08

0 0 0 1				dst (nz)				1 1 1 1				src (16)				TRUNC	dst,b	r[dst] = r[dst]:f:0
0 0 0 1				dst (nz)				1 1 1 0				src (16)				SXT	dst,b	r[dst] = sx(r[dst]:f:0)
0 0 0 1				dst (nz)				1 1 0 1				src (16)				BTRUNC	dst,b	pc=pc+((r[dst]:f:0)<<1)
0 0 0 1				dst (nz)				1 1 0 0				src (8)				ADDSI	dst,c	r[dst] = r[dst] + c

C.1.9. Two Register Format (See Chapter 10)

07	06	05	04	03	02	01	00	15	14	13	12	11	10	09	08

0 0 0 1				dst (nz)				1 0 1 1				src (nz)				AND	dst,src	r[dst] =(r[dst] ∧ r[src])
0 0 0 1				dst (nz)				1 0 1 0				src (nz)				OR	dst,src	r[dst] =(r[dst] ∨ r[src])
0 0 0 1				dst (nz)				1 0 0 1				src (0)				EQU	dst,src	r[dst] =(r[dst] ≡ r[src])
0 0 0 1								1 0 0 0								—
0 0 0 1				dst (x)				0 1 1 1				src (0)				ADDC	dst,src	r[dst]=r[dst]+r[src]+C
0 0 0 1				dst (x)				0 1 1 0				src (0)				SUBB	dst,src	r[dst]=r[dst]-r[src]-~C

Synonyms

07	06	05	04	03	02	01	00	15	14	13	12	11	10	09	08

0 0 0 1				dst (nz)				1 0 0 1				0 0 0 0				NOT	dst	r[dst] = ~r[dst]
0 0 0 1				dst (x)				0 1 1 1				src=dst				ROL	dst	r[dst]= (r[dst]<<1)+C

C.1.10. Special Format (See Chapter 11)

07	06	05	04	03	02	01	00	15	14	13	12	11	10	09	08

0 0 0 1				dst (nz)				0 1 0 1				src				ADJUST	dst,src	r[dst] = r[dst]+adj[src]
0 0 0 1				dst (nz)				0 1 0 0				src (pc)				PLUS	dst,src	r[dst] = r[dst]+r[src]
0 0 0 1				dst (x)				0 0 1 1				src				COGET	dst,src	r[dst] = co[src]
0 0 0 1				srcx (0)				0 0 1 0				src				COSET	srcx,src	co[src] = r[srcx]





0 0 0 1				dst (pc)				0 0 0 1				src				CPUGET	dst,src	r[dst] = cpu[src]
0 0 0 1				srcx (0)				0 0 0 0				src				CPUSET	srcx,src	cpu[src] = r[srcx]

Synonyms

07	06	05	04	03	02	01	00	15	14	13	12	11	10	09	08

0 0 0 1				0 0 0 0				0 0 0 1				0 0 0 1				RTT	pc = tpc; level = prior

C.1.11. Branch Format (See Chapter 12)

07	06	05	04	03	02	01	00	15	14	13	12	11	10	09	08

0 0 0 0 1 1 1 1								disp								BGTU	ea	if (C ∧ ~Z) pc = ea
0 0 0 0 1 1 1 0								disp								BGT	ea	if ((N⊕V)∧~Z) pc=ea
0 0 0 0 1 1 0 1								disp								BGE	ea	if (N ⊕ V) pc = ea
0 0 0 0 1 1 0 0								disp								BCR	ea	if (~C) pc = ea
0 0 0 0 1 0 1 1								disp								BVR	ea	if (~V) pc = ea
0 0 0 0 1 0 1 0								disp								BZR	ea	if (~Z) pc = ea

07	06	05	04	03	02	01	00	15	14	13	12	11	10	09	08

0 0 0 0 1 0 0 1								disp								BNR	ea	if (~N) pc = ea
0 0 0 0 1 0 0 0																—

0 0 0 0 0 1 1 1								disp								BLEU	ea	if (~C ∨ Z) pc = ea
0 0 0 0 0 1 1 0								disp								BLE	ea	if ((N ≡ V)∨Z) pc = ea
0 0 0 0 0 1 0 1								disp								BLT	ea	if (N ≡ V) pc = ea
0 0 0 0 0 1 0 0								disp								BCS	ea	if (C) pc = ea
0 0 0 0 0 0 1 1								disp								BVS	ea	if (V) pc = ea
0 0 0 0 0 0 1 0								disp								BZS	ea	if (Z) pc = ea
0 0 0 0 0 0 0 1								disp								BNS	ea	if (N) pc = ea
0 0 0 0 0 0 0 0								disp								BR	ea	pc = ea

Synonyms

07	06	05	04	03	02	01	00	15	14	13	12	11	10	09	08

0 0 0 0 1 1 0 0								disp								BLTU	ea	if (~C) pc = ea
0 0 0 0 1 0 1 0								disp								BNE	ea	if (~Z) pc = ea

0 0 0 0 0 1 0 0								disp								BGEU	ea	if (C) pc = ea
0 0 0 0 0 0 1 0								disp								BEQ	ea	if (Z) pc = ea
0 0 0 0 0 0 0 0								0 0 0 0 0 0 0 0								NOP

C.2. Alphabetical Listing, Binary Format

0 0 1 1

dst (x)

s1 (nz)

s2 (nz)

ADD

dst,s1,s2

r[dst] = r[s1] + r[s2]

0 0 0 1

dst (x)

0 1 1 1

src (0)

ADDC

dst,src

r[dst]=r[dst]+r[src]+C

1 1 1 1

dst (x)

0 1 1 0

x (pc)

ADDI

dst,x,disp

r[dst] = ea

0 0 0 1

dst (nz)

1 1 0 0

src (8)

ADDSI

dst,c

r[dst] = r[dst] + c

1 0 1 0

dst (nz)

s1 (0)

s2 (16)

ADDSL

dst,s1,s

r[dst]=r[dst]<<s + r[s1]

1 0 0 1

dst (x)

s1 (0)

s2 (16)

ADDSR

dst,s1,s

r[dst]=(r[dst]+r[s1])>>s

1 0 0 0

dst (x)

s1 (0)

s2 (16)

ADDSRU

dst,s1,s

r[dst]=(r[dst]+r[s1])>>>s

0 0 0 1

dst (nz)

0 1 0 1

src

ADJUST

dst,src

r[dst]=r[dst]+adj[src]

0 0 0 1

dst (nz)

1 0 1 1

src (nz)

AND

dst,src

r[dst]=(r[dst] ∧ r[src])

0 0 0 0 1 - 0 -

disp

BBR

if (reset) pc = ea

0 0 0 0 0 - 0 -

disp

BBS

if (set) pc = ea

0 0 0 0 1 1 0 0

disp

BCR

if (~C) pc = ea

0 0 0 0 0 1 0 0

disp

BCS

if (C) pc = ea

0 0 0 0 0 0 1 0

disp

BEQ

if (Z) pc = ea

0 0 0 0 1 1 0 1

disp

BGE

if (N ⊕ V) pc = ea

0 0 0 0 0 1 0 0

disp

BGEU

if (C) pc = ea

0 0 0 0 1 1 1 0

disp

BGT

if((N⊕V)∧~Z)pc=ea

0 0 0 0 1 1 1 1

disp

BGTU

if (C ∧ ~Z) pc = ea

1 1 1 1 0 0 0 0

1 1 1 0

x (pc)

BITTST

x,31

b = 31

1 0 0 1 0 0 0 0

s1 (0)

s2 (16)

BITTST

dst,s-1

0 ≤ b ≤ 15: s = b + 1

1 0 1 1 0 0 0 0

s1 (nz)

s2 (16)

BITTST

s1,31-s

16 ≤ b ≤ 30: s = 31 - b

0 0 0 0 0 1 1 0

disp

BLE

if((N ≡ V)∨Z) pc=ea

0 0 0 0 0 1 1 1

disp

BLEU

if (~C ∨ Z) pc = ea

0 0 0 0 0 1 0 1

disp

BLT

if (N ≡ V) pc = ea

0 0 0 0 1 1 0 0

disp

BLTU

if (~C) pc = ea

0 0 0 0 1 0 1 0

disp

BNE

if (~Z) pc = ea

0 0 0 0 1 0 0 1

disp

BNR

if (~N) pc = ea

0 0 0 0 0 0 0 1

disp

BNS

if (N) pc = ea

0 0 0 0 0 0 0 0

disp

pc = ea

0 0 0 1

dst (nz)

1 1 0 1

src (16)

BTRUNC

dst,b

pc=pc+((r[dst]:f:0)<<1)

0 0 0 0 1 0 1 1

disp

BVR

if (~V) pc = ea

0 0 0 0 0 0 1 1

disp

BVS

if (V) pc = ea

0 0 0 0 1 0 1 0

disp

BZR

if (~Z) pc = ea

0 0 0 0 0 0 1 0

disp

BZS

if (Z) pc = ea

1 1 0 1

dst (nz)

0 0 0 0 0 0 0 0

CLR

dst

r[dst] = 0

0 0 1 0

0 0 0 0

s1 (0)

s2 (nz)

CMP

s1,s2

1 1 1 1

0 0 0 0

0 1 1 0

x (pc)

CMPI

x,-disp

0 0 0 1

dst (x)

0 0 1 1

src

COGET

dst,src

r[dst] = co[src]

0 0 0 1

srcx (0)

0 0 1 0

src

COSET

srcx,src

co[src] = r[srcx]

0 0 0 1

dst (pc)

0 0 0 1

src

CPUGET

dst,src

r[dst] = cpu[src]

0 0 0 1

srcx (0)

0 0 0 0

src

CPUSET

srcx,src

cpu[src] = r[srcx]

0 0 0 1

dst (nz)

1 0 0 1

src (0)

EQU

dst,src

r[dst]=(r[dst]≡r[src])

0 1 0 1

dst (x)

s1 (nz)

s2 (0)

EXTB

dst,s1,s2

r[dst] = r[s1]:b+7:b

0 1 0 0

dst (x)

s1 (nz)

s2 (0)

EXTH

dst,s1,s2

r[dst] = r[s1]:b+15:b

1 1 1 1

dst (x)

0 0 1 1

x (pc)

JSR

dst,x,disp

r[dst] = pc; pc = ea

1 1 1 1

dst (x)

1 0 1 1

x (pc)

JSRS

dst,x

r[dst] = pc; pc = ea

1 1 1 1

0 0 0 0

0 0 1 1

x (pc)

JUMP

x,disp

pc = ea

1 1 1 1

0 0 0 0

1 0 1 1

x (pc)

JUMPS

dst,x

pc = ea

1 1 1 1

dst (nz)

0 1 1 1

x (pc)

LEA

dst,x,disp

r[dst] = ea

1 1 1 1

dst (x)

0 1 1 0

x (pc)

LEACC

dst,x,disp

r[dst] = ea

1 1 1 0

dst (pc)

const:7:0

LIL

dst,const

r[dst] = sx(const)

1 1 0 1

dst (nz)

const

LIS

dst,const

r[dst] = sx(const)

1 1 1 1

dst (pc)

0 1 0 1

x (pc)

LOAD

dst,x,disp

r[dst] = m[ea]

1 1 1 1

dst (x)

0 1 0 0

x (pc)

LOADCC

dst,x,disp

r[dst] = m[ea]

1 1 1 1

dst (x)

1 0 0 1

x (nz)

LOADL

dst,x

r[dst] = m[ea]

1 1 1 1

dst (pc)

1 1 0 1

x (pc)

LOADS

dst,x

r[dst] = M[ea]

1 1 1 1

dst (x)

1 1 0 0

x (pc)

LOADSCC

dst,x

r[dst] = M[ea]

1 1 1 1

dst (nz)

1 1 1 1

x (pc)

MOVE

dst,x

r[dst] = ea

1 1 1 1

dst (x)

1 1 1 0

x (pc)

MOVECC

dst,x

r[dst] = ea

1 0 1 1

dst (x)

s1 (nz)

s2 (16)

MOVESL

dst,s1,s

r[dst] = r[s1]<<s

0 0 1 0

dst (x)

0 0 0 0

s2 (nz)

NEG

dst,s2

r[dst] = 0 – r[s2]

0 0 0 0 0 0 0 0

NOP

0 0 0 1

dst (nz)

1 0 0 1

0 0 0 0

NOT

dst

r[dst] = ~r[dst]

0 0 0 1

dst (nz)

1 0 1 0

src (nz)

dst,src

r[dst] =(r[dst] ∨ r[src])

1 1 0 0

dst (nz)

const

ORIS

dst,const

r[dst]=r[dst]<<8∨const

0 0 0 1

dst (nz)

0 1 0 0

src (pc)

PLUS

dst,src

r[dst]=r[dst]+r[src]

0 0 0 1

dst (x)

0 1 1 1

src=dst

ROL

dst

r[dst]= r[dst]<<1+C

0 0 0 1

0 0 0 0

0 0 0 1

RTT

pc = tpc; level = prior

1 0 1 0

dst (nz)

0 0 0 0

s2 (16)

dst,s

r[dst] = r[dst] << s

1 0 0 1

dst (x)

0 0 0 0

s2 (16)

dst,s

r[dst] = r[dst] >> s

1 0 0 0

dst (x)

0 0 0 0

s2 (16)

SRU

dst,s

r[dst] = r[dst] >>> s

1 1 1 1

srcx (0)

0 0 1 0

x (pc)

STORE

srcx,x,disp

m[ea] = r[srcx]

1 1 1 1

srcx (0)

1 0 0 0

x (nz)

STOREC

srcx,x

if ok, m[ea] = r[srcx]

1 1 1 1

srcx (0)

1 0 1 0

x (nz)

STORES

srcx,x

m[ea] = r[srcx]

0 1 1 1

dst (nz)

s1 (0)

s2 (0)

STUFFB

dst,s1,s2

r[dst]:b+7:b = r[s1]

0 1 1 0

dst (nz)

s1 (0)

s2 (0)

STUFFH

dst,s1,s2

r[dst]:h+15:h = r[s1]

0 0 1 0

dst (x)

s1 (0)

s2 (nz)

SUB

dst,s1,s2

r[dst] = r[s1] – r[s2]

0 0 0 1

dst (x)

0 1 1 0

src (0)

SUBB

dst,src

r[dst]=r[dst]-r[src]-~C

07	06	05	04	03	02	01	00	15	14	13	12	11	10	09	08

0 0 0 1				dst (nz)				1 1 1 0				src (16)				SXT	dst,b	r[dst] = sx(r[dst]:f:0)

1 1 1 1				0 0 0 0				0 1 0 0				x (pc)				TEST	x,disp
1 1 1 1				0 0 0 0				1 1 1 0				x (pc)				TESTR	x
1 1 1 1				0 0 0 0				1 1 0 0				x (pc)				TESTS	x
0 0 0 1				dst (nz)				1 1 1 1				src (16)				TRUNC	dst,b	r[dst] = r[dst]:f:0

C.3. Alphabetical Listing, Assembly Format and Index



ADD	dst,s1,s2	r[dst] = r[s1] + r[s2]	x	nz	nz	N	Z	V	C	8.2
ADDC	dst,src	r[dst]=r[dst]+r[src]+C	x		0	N	Z	V	C	10.3
ADDI	dst,x,disp	r[dst] = ea	x		pc	N	Z	V	C	3.2
ADDSI	dst,c	r[dst] = r[dst] + c	nz		8	N	Z	V	C	9.3
ADDSL	dst,s1,s	r[dst] = r[dst]<<s + r[s1]	nz	0	16	N	Z	V	C	6.2
ADDSR	dst,s1,s	r[dst]=(r[dst]+r[s1])>>s	x	0	16	N	Z	V	C	6.3
ADDSRU	dst,s1,s	r[dst]=(r[dst]+r[s1])>>>s	x	0	16	N	Z	V	C	6.3
ADJUST	dst,src	r[dst] = r[dst]+adj[src]	nz			-	-	-	-	11.2
AND	dst,src	r[dst] =(r[dst] ∧ r[src])	nz		nz	N	Z	0	0	10.2

BBR	ea	if (reset) pc = ea				-	-	-	-	6.4
BBS	ea	if (set) pc = ea				-	-	-	-	6.4
BCR	ea	if (~C) pc = ea				-	-	-	-	12.2
BCS	ea	if (C) pc = ea				-	-	-	-	12.2
BEQ	ea	if (Z) pc = ea				-	-	-	-	12.2
BGE	ea	if (N ⊕ V) pc = ea				-	-	-	-	12.2
BGEU	ea	if (C) pc = ea				-	-	-	-	12.2
BGT	ea	if ((N⊕V)∧~Z) pc=ea				-	-	-	-	12.2
BGTU	ea	if (C ∧ ~Z) pc = ea				-	-	-	-	12.2
BITTST	x,31	b = 31			(pc)	N	Z	0	0	6.4
BITTST	dst,s-1	0 ≤ b ≤ 15: s = b + 1		0	16	N	Z	V	C	6.4
BITTST	s1,31-s	16 ≤ b ≤ 30: s = 31 - b		nz	16	N	Z	V	C	6.4
BLE	ea	if ((N ≡ V)∨Z) pc = ea				-	-	-	-	12.2
BLEU	ea	if (~C ∨ Z) pc = ea				-	-	-	-	12.2
BLT	ea	if (N ≡ V) pc = ea				-	-	-	-	12.2
BLTU	ea	if (~C) pc = ea				-	-	-	-	12.2
BNE	ea	if (~Z) pc = ea				-	-	-	-	12.2
BNR	ea	if (~N) pc = ea				-	-	-	-	12.2
BNS	ea	if (N) pc = ea				-	-	-	-	12.2
BR	ea	pc = ea				-	-	-	-	12.3
BTRUNC	dst,b	pc=pc+((r[dst]:f:0)<<1)	nz		16	-	-	-	-	9.3
BVR	ea	if (~V) pc = ea				-	-	-	-	12.2
BVS	ea	if (V) pc = ea				-	-	-	-	12.2
BZR	ea	if (~Z) pc = ea				-	-	-	-	12.2
BZS	ea	if (Z) pc = ea				-	-	-	-	12.2

CLR	dst	r[dst] = 0	nz			-	-	-	-	5.2

CMP	s1,s2			0	nz	N	Z	V	C	8.2
CMPI	x,-disp				pc	N	Z	V	C	3.2
COGET	dst,src	r[dst] = co[src]	x			N	Z	V	C	11.4
COSET	srcx,src	co[src] = r[srcx]	0			-	-	-	-	11.4
CPUGET	dst,src	r[dst] = cpu[src]	pc			-	-	-	-	11.5
CPUSET	srcx,src	cpu[src] = r[srcx]	0			-	-	-	-	11.5

EQU	dst,src	r[dst] =(r[dst] ≡ r[src])	nz		0	N	Z	0	0	10.2
EXTB	dst,s1,s2	r[dst] = r[s1]:b+7:b	x	nz	0	N	Z	0	0	7.3
EXTH	dst,s1,s2	r[dst] = r[s1]:b+15:b	x	nz	0	N	Z	0	0	7.3

JSR	dst,x,disp	r[dst] = pc; pc = ea	x		pc	-	-	-	-	3.4
JSRS	dst,x	r[dst] = pc; pc = ea	x		pc	-	-	-	-	2.4
JUMP	x,disp	pc = ea			pc	-	-	-	-	3.4
JUMPS	x	pc = ea			pc	-	-	-	-	2.4

LEA	dst,x,disp	r[dst] = ea	nz		pc	-	-	-	-	3.2
LEACC	dst,x,disp	r[dst] = ea	x		pc	N	Z	V	C	3.2
LIL	dst,const	r[dst] = sx(const)	pc			-	-	-	-	4.2
LIS	dst,const	r[dst] = sx(const)	nz			-	-	-	-	5.2
LIW	dst,const	r[dst] = const	nz			-	-	-	-	5.2
LOAD	dst,x,disp	r[dst] = m[ea]	pc		pc	-	-	-	-	3.3
LOADCC	dst,x,disp	r[dst] = m[ea]	x		pc	N	Z	V	C	3.3
LOADL	dst,x	r[dst] = m[ea]	x		pc	N	Z	V	C	2.6
LOADS	dst,x	r[dst] = M[ea]	pc		pc	-	-	-	-	2.3
LOADSCC	dst,x	r[dst] = M[ea]	x		pc	N	Z	V	C	2.3

MOVE	dst,x	r[dst] = ea	nz		pc	-	-	-	-	2.2
MOVECC	dst,x	r[dst] = ea	x		pc	N	Z	V	C	2.2
MOVESL	dst,s1,s	r[dst] = r[s1]<<s	x	nz	16	N	Z	V	C	6.2

NEG	dst,s2	r[dst] = 0 – r[s2]	x		nz	N	Z	V	C	8.2
NOP						-	-	-	-	12.3
NOT	dst	r[dst] = ~r[dst]	nz			N	Z	0	0	10.2

OR	dst,src	r[dst] =(r[dst] ∨ r[src])	nz		nz	N	Z	0	0	10.2
ORIS	dst,const	r[dst]=r[dst]<<8∨const	nz			-	-	-	-	5.2
PLUS	dst,src	r[dst] = r[dst]+r[src]	nz			-	-	-	-	11.3
ROL	dst	r[dst]= r[dst]<<1+C	x			N	Z	V	C	10.3
RTT		pc = tpc; level = prior				-	-	-	-	11.5

SL	dst,s	r[dst] = r[dst] << s	nz		16	N	Z	V	C	6.2
SR	dst,s	r[dst] = r[dst] >> s	x		16	N	Z	V	C	6.3
SRU	dst,s	r[dst] = r[dst] >>> s	x		16	0	Z	V	C	6.3
STORE	srcx,x,disp	m[ea] = r[srcx]	0		pc	-	-	-	-	3.5
STOREC	srcx,x	if ok, m[ea] = r[srcx]	0		nz	0	0	V	0	2.6
STORES	srcx,x	m[ea] = r[srcx]	0		nz	-	-	-	-	2.5
STUFFB	dst,s1,s2	r[dst]:b+7:b = r[s1]	nz	0	0	-	-	-	-	7.2
STUFFH	dst,s1,s2	r[dst]:h+15:h = r[s1]	nz	0	0	-	-	-	-	7.2
SUB	dst,s1,s2	r[dst] = r[s1] – r[s2]	x	0	nz	N	Z	V	C	8.2
SUBB	dst,src	r[dst]=r[dst]-r[src]-~C	x		0	N	Z	V	C	10.3
SXT	dst,b	r[dst] = sx(r[dst]:f:0)	nz		16	N	Z	V	C	9.2

TEST	x,disp				pc	N	Z	V	C	3.3
TESTR	x				pc	N	Z	V	C	2.2
TESTS	x				pc	N	Z	V	C	2.3
TRUNC	dst,b	r[dst] = r[dst]:f:0	nz		16	0	Z	V	C	9.2

C. Instruction Set Summary and Index

Contents

C.1. Instruction Set Summary

C.1.1. Short Memory Reference Format (See Chapter 2)

Synonyms

C.1.2. Memory Reference Format (See Chapter 3)

Synonyms

C.1.3. Long Immediate Format (See Chapter 4)

C.1.4. Short Immediate Format (See Chapter 5)

Synonyms

C.1.5. Shift Format (See Chapter 6)

Synonyms

C.1.6. Byte and Halfword Format (See Chapter 7)

C.1.7. Add and Subtract Format (See Chapter 8)

Synonyms

C.1.8. Short Constant Format (See Chapter 9)

C.1.9. Two Register Format (See Chapter 10)

Synonyms

C.1.10. Special Format (See Chapter 11)

Synonyms

C.1.11. Branch Format (See Chapter 12)

Synonyms

C.2. Alphabetical Listing, Binary Format

C.3. Alphabetical Listing, Assembly Format and Index