10. Two Register Instructions

Contents

10.1. Two Register Format
10.2. Bitwise Logical Operations
10.3. Extended Precision Arithmetic

10.1. Two Register Format

The two register arithmetic format instructions are 16 bits each, specifying one source register r[src] and one destination register r[dst]. All instructions in this group combine the value in r[src] with the value in r[dst], changing only the latter and the condition codes.

10.2. Bitwise Logical Operations

AND, OR and EQU (equivalent) operations combine each bit of the source register with the corresponding bit of the destination register using the indicated boolean operation.

For AND, each bit of r[dst] will be set only if it was already set there and the corresponding bit was also set in r[src].

For OR, each bit of r[dst] will be set if it was already set there or if the corresponding bit was also set in r[src].

Both AND and OR require that the src and dst be nonzero. If r[0] is used, it will cause an instruction trap (see Chapter 13). Assemblers should flag use of r[0] as an error.

For EQU, each bit of r[dst] will be set only if the original value of that bit was equal to the corresponding bit in r[src]. In logical terms, EQU computes the inverse of the exclusive or of its oprands because (a≡b) = ~(a⊕b).

Because ~x (not x) is the same as x≡0 (comparing the bits of x with zero), use of r[0] as a source operand is legal with EQU and it is interpreted as holding constant zero. Assemblers should support NOT Rd as a synonym for EQU Rd,R0.

Because EQU computes the inverse of exclusive or, the exclusive-or of two operands can be computed using a combination of NOT and EQUIV. For example, the following sequence exclusive-ors r[4] with r[3]:

        EQUIV   R3,R4
        NOT     R3

10.3. Extended Precision Arithmetic

ADDC (add with carry) and SUBB (subtract with borrow) are used to do integer arithmetic on quantities longer than 32 bits. These add or subtract one register from another taking into account the carry or borrow bit left over from the addition or subtraction of the less significant bits.

The condition codes (see Section 1.3.4.1) reflect the extended precision result. N is set if the result is negative, Z is set if the entire result is zero; that is, it is reset if the result was nonzero, and it remains set only if the result was zero and it was already set. V is set if two's complement overflow occurred, and C is set if there was a carry out of the most significant bit (equivalent to no borrow out of the most significant bit).

The following sequence starting with a regular ADD instruction (see Section 8.2) for the least significant 32 bits does a 96-bit register-to-register sum. Here, we store each 96-bit operand in 3 consecutive 32-bit registers, with the least significant 32 bits in the lowest numbered registers. The destination operand is in r[3-5] while the source operand is in r[6-8]:

	ADD	R3,R3,R6	; add low 32 bits
	ADDC	R4,R7		; add middle 32 bits
	ADDC	R5,R8		; add high 32 bits

ADDC sets the BCD-carry bits in the processor status word. (see Section 1.3.4.1). As a result, in combination with ADD and ADJUST it can be used to do high-precision BCD or excess-3 arithmetic (see Section 11.2).

For both ADDC and SUBB, src may be zero, in which case r[0] is taken as the constant zero. As a result, in combination with ADDSL The following sequence rotates the 32 bit value in r[1] 1 bit left, so that the old value of the sign bit goes into the least significant bit:

	ADDSL	R3,R0,1		; shift 1 bit left
	ADDC	R3,R0		; bring carry around

The ADDC instruction alone, with src=dst, rotates the 33 bit value composed of the source register concatenated with the condition code register 1 bit left. This is useful for left-shifting multi-word quantities, so ssemblers should treat ROL dst (rotate left) as a synonym for ADDC dst,dst.