The University of Iowa's DEC PDP-8

Restoration Log

Part of the UI-8 pages
by Douglas W. Jones
THE UNIVERSITY OF IOWA Department of Computer Science



This is a chronological log of the progress restoring the University of Iowa's PDP-8 computer. Entries are added at the end as work progresses. Click on any thumbnail image to see full-sized image.

Feb 12, 2018, W034 Cable

Bug 4 and Bug 64: Given that quite a bit of the the CPU seems to be working, we began to investigate the memory. One of the first things we noticed was that the Maintenance Manual (Feb. 1966 Ed., pages 10-70 to 10-76) documents 7 W034 cables between the CPU and memory half backplanes, but there are only 6 present. The missing cable (page 10-76) would connect backplane slots PD02 and MD35. While we have not fully understood the signals that pass through the various cables, this makes it more pressing that we attempt to manufacture replacements for these cables.

  thumbnail image   thumbnail image  
W034D cable connector
We began by taking additional photos of the board that serves as a connector on each end of the cable, supplementing the photo taken on May. 27, 2014. We took key dimensions from the specifications in the Digital Logic Handbook, 1967 Edition, page 225, and measured the others from the photos. The diagrams to the left show our results.

Having done this, we found that Vince Slyngstad has already done much of this. See his CAD Project Files, indexed under ./DEC/Wxxx/W034: Flexprint, 16 connections on "B" side 10 ohms on A2, B2. This includes photos, schematics and board layouts for the W034D, W034H, and W034X. The latter is a modern redesign, while the two former are historical DEC designs. We need to evaluate his modern design to see if it meets our requirements.

Feb 14, 2018, Disconnect mag tape interface

Bug 31: After poking around the ADC rack, we decided to remove the locally built magnetic tape drive interface from the ADC rack. Removal of this device interface is complicated by the fact that it is not daisy-chained into the I/O bus the way off-the-shelf device interfaces were done. Instead, wire-wrap wiring has been used to tap into the I/O bus connectors in the analog to digital converter backplane immediately above it. In addition, spare slots in that backplane have been used for a few additional logic boards and interface plugs needed for the tape drive.

  thumbnail image  
Using an unwrapping tool
The first step was to remove the wires that connected between the ADC and the tape-drive interface, using the unwrapping end of a standard wire-wrap tool. All of DEC's factory wiring and field-changes were done with 24-gauge wire, almost all of it with yellow insulation. The wires we removed were a mix yellow of 30-gauge wire (with a woefully inadequate number of wraps on each pin) and some red and blue 24-gauge wire. We documented every wire removed in the log book, using DEC's standard coordinate system:

Pin E12B refers to a pin on row E (counting from the top), slot 12 (counting from the left side of the wiring side of the backplane) pin E (as printed in white on the wiring side of the black connector blocks). The tape-drive interface was mostly in rows E and F, with wiring to a few spare slots in row D and one slot (used for a cable connector) in row C. We logged the wire color, source pin and destination pin for each wire we removed.

We also pulled the cables that connected the tape-drive control panel to slots in the backplane segments involved. The wires at one end of this cable were soldered to parts of the control panel, another end of this cable ended in cut-off wires that apparently went to the tape drive, while the third and forth ends of this cable went to card-edge connectors plugged into the backplane. At least one of these was almost certainly plugged into the wrong backplane slot, but we wrote on each card-edge connector the slot number into which it had been plugged.

Feb 21, 2018, Remove mag tape interface, memory sleuthing

  thumbnail image  
Removing rows E and F
Bug 31: We continued removing wires, documenting the removals in the log book, until we thought no wires remained between rows A though D and rows E and F of the top backplane section of the ADC rack, and then we unscrewed the mounting panel for rows E and F, only to find that one wire remained. It turns out that the power connections to rows E and F was done by wire-wrapped wires from rows C and D instead of using the faston connector tabs on the left side of the mounting panels.

With the final wire removed, we were able to pull the remains of the home-brew tape-drive interface from the rack. We believe that some boards on the lower right end of row D are also part of this home-brew interface. Wiring to those boards from rows E and F has been removed, but the local wiring on row D remains in place.

The home-made tape drive control panel directly below rows E and F had one remaining cable still connecting it to other parts of the rack. In this case, to a block of relays attached to a board cantelevered out from the back of the topmost panel on the back of the rack. We simply cut the wires from the cable to this block of relays. The colors of the cut wires should be sufficient to allow reversing this change, should someone want to do so. We will tag all removed parts to allow this.

Bug 64: We tracked down David Gesswein's photos of a table-top PDP-8 he restored. These photos of his show the cabling between the two half backplanes:

These photos clearly show only 6 cables, all from Px01 to Mx36 (for x from A to F). The photos do not show the 7th cable connecting PD02 to MD35. On Feb. 12, 2018 we had speculated that perhaps this missing cable was the cause of our memory problems. Apparently, this is not the case. It appears that this cable is not needed on machines with only 4K of memory. Therefore, cable replacement moves down on our list of prioritie, but remains there because of the decayed nature of the 6 cables we have.

  thumbnail image  
Current limiters
The Maintenance Manual (Feb. 1966 Ed., page 9-12) says that the first thing we need to do when checking the memory is to measure and adjust the read/write current and the inhibit current. These currents are to be measured at the wire from the current-determining resistor to the appropriate backplane module. Where are these resistors? The explanation of the memory operation given in Figure 4-4 on page 4-6 of the Maintenance Manual shows an 80&Ohm; "current determining resistor" in the circuit, but it doesn't say where to look for it.

Looking at the detailed drawings in the Maintenance Manual, BS-D-8M-0-12 X Axis Selection, BS-D-8M-0-13 Y Axis Selection and BS-D-AM-0-15 Sense Amps, Inhibit Drivers, and Memory Control all show the detailed locations of the boards involved and document the role of 80&Ohm; current limiting resistors, but they don't show where the resistors are. We found these resistors lurking on an aluminum heat sink behind the balun network boards on the front-side of the core stack. See photo. These are all 80&Ohm; 10W 1% precision resistors. We infer from the fact that two of them have small resistor capacitor networks serving as shunts that those two are the X and Y axis current limiters attached to the G209 modules, while the other 13 resistors each serve one of the G208 inhibit drivers (the 13th resistor is a spare on our system since we don't have the memory parity option.) Note that this little RC network isn't documented in the maintenance manual.

A second problem we will face is that the above-cited manual pages all refer to handwritten notes that should be on the label of our memory module. We have found no such notes. The Dalby Datormuseum has a photo of the label on their PDP-8 memory that gives a R/W (select) current of 325mA and an inhibit current of 305mA, so if we cannot find documentation for our machine, we at least know reasonable values for these currents.

Apr 4, 2018, Add test points to memory resistors

  thumbnail image     thumbnail image  
Instrumented current limiters
Bug 64: As noted on Feb. 21, we need to measure the current through the 80Ω current limiting resistors in the inhibit and select circuits. The manual says to do this by carefully fishing one of the yellow wires from the resistors out of the backplane in order to attach a current probe to it. This is something appropriate to do one or twice in the life of a machine, but if we want to preserve this machine for the long haul, we don't want to repeatedly flex any of the backplane wiring.

An alternative way to measure the current through any of the 80Ω resistors is to simply measure the voltage across the resistor, but they are inaccessible behind the circuit boards holding the memory balun coils. To allow this method of measuring the current, we attached a set of 4 test points at an accessible location directly behind the plate on which the resistors are mounted and wired a pair of test points across one of the resistors limiting the select current and one limiting the inhibit current.

Apr 11, 2018, Calibrate scope

  thumbnail image   thumbnail image  
Inhibit and R/W select currents
Bug 64: We set up the scope, powered from a DC supply so that it was floating relative to ground, using the methodology discussed on Dec. 16, 2014. This allowed us to take current measurements across the 80Ω current limiting resistors in the memory circuit, and then we observed the waveforms shown here. We had extreme difficulty getting the scope to trigger properly when operating at 1µsec/division, and the current magnitudes we measured were far too low.

The good news is that we got waveforms on both the R/W select and inhibit currents. The waveforms start when you hit the CONT (continue) switch on the front panel, and they stop when you hit HALT. This means that the key memory control signals from the CPU are reaching the memory. This is the first time we have confirmed this.

Checking the scope by using its internal calibration oscillator, we found that it was way out of calibration, so we spent the rest of the afternoon searching the scope manual for calibration instructions and then doing what we could to calibrate it using its internal calibration oscillator and a DC voltmeter. The scope was, in fact, way out of calibration. The internal 10V DC supply from which the scope derives all of its other voltages was under 8 volts. Adjusting this and then bringing everything else into balance seems to have made the scope trigger circuitry work much better.

Apr 18, 2018, Examine memory current waveforms

  thumbnail image   thumbnail image  
Inhibit and R/W select currents
0.5µsec/div hoiz; 10v/div vertical
Bug 64: We measured the Inhibit current and R/W select current. This was a bit difficult because the scope's graticule illumination only works when the scope is running from AC power. Oblique illumination with flashlight worked as a poor substitute.

The Dalby Datormuseum photo of their their PDP-8 memory label that gives a R/W select current of 325mA and an inhibit current of 305mA, so the values we see are in the right ballpark.

Note that the period of the Inhibit and select waveforms is 1.5 microseconds, exactly the memory cycle time advertised in the. Maintenance Manual (1965 ed, page 1-1).

Because this is core memory, each memory cycle consists of a read/erase subcycle where the contents of the addressed word are destructively read, followed by a write/restore subcycle where the data just read is returned. The inhibit line is only pulsed during a write/restore cycle, and then, only when the value written is zero. Since we are currently reading all zeros from memory on every cycle, the inhibit line is pulsed once per cycle. This looks right.

The R/W select lines are more complex. During the read/erase subcycle, the read select line should be pulsed, and during the write/restore subcycle, the write select line should be pulsed. These pulses are mixed by the balun networks on the G603 boards attached directly to the core memory module to produce a negative current pulse for the read/erase subcycle and a positive pulse for the write/restore subcycle. Both the read and write select lines in each pair share a single current limiting resistor, as shown in the Maintenance Manual (1965 ed, Figure 4-4, page 4-6). Thus, we should see two current pulses during each memory cycle, one for the read/erase subcycle, and one for the write/restore subcycle. We do see two pulses per subcycle, but they are strangely brief and they have different magnitudes! Something seems amiss.

  thumbnail image  
Inhibit logic signal
  thumbnail image   thumbnail image  
Read and Write logic signals
0.5µsec/div hoiz; 1.0v/div vertical
We checked the logic levels on the Inhibit, Read and Write logic levels that are inputs to the R/W select drivers and Inhibit drivers. Comparing these signals with the information shown in the Maintenance Manual (1965 ed, Figure 4-5, page 4-11). The inhibit signal looks right (although the waveforms shown in the manual are shown inverted relative to the scope display). Read is indeed a longer pulse than write, explaining some of the assymetry of the combined waveform on the R/W select current. This does not explain the low amplitude of the current for the shorter of the two subcycles.

We used internal triggering for these measurements, so do not read any meaning into the phase differences on the scope displays.