12. Branch Instructions

Contents

12.1. Branch Format
12.2. Conditional Branch
12.3. Branch

12.1. Branch Format

Branch format instructions are 16 bits each, incorporating a 4-bit branch condition and an 8 bit 2's complement branch displacement. For all of these instructions, the effective address is formed by adding twice the displacement to the program counter (see Section 1.3.2).

This allows branches to be taken to any instruction halfword within a 256 halfword range. Because the program counter is incremented after instruction fetch (see Section 1.4), a displacement of zero refers to the instruction immediately after the branch. Positive displacements refer to later instructions, negative displacements refer to earlier ones.

Hawk assemblers should automatically compute the displacement when given the symbolic label of the destination. Thus, if X is the label on a nearby location BR X should transfer control to that location. The following code will generate a branch displacement of zero:

        BR      L
L:

Branch instructions with a displacement of –1 create infinite loops. As such, Hawk assemblers should report disp=11111111 as an error; future versions of the Hawk may assign other meanings to these.

There is actually only one branch instruction, with the c field selecting one of 15 tests to be made on the condition codes (see Section 1.3.4.1). Hawk assemblers should use a different mnemonic for each of the 15 possible branches. Also note that c=1000 is unassigned and reserved for future use.

12.2. Conditional Branch

The conditional branch group of instructions allows 14 combinations of condition code settings to be tested (see Section 1.3.4.1). There are two groups of seven branch instructions, where the second group is identical to the first, except that the condtion tested is inverted. Both the format of this instruction and the use made of the condition codes date back to 1970, when they were used for the DEC PDP-11. Both the Intel 80x86 and the Motorola 680x0 families also copied their branch instructions from the PDP-11.

Hawk assemblers should define the following additional synonyms for some of the above conditional branch instructions:

The BNS (branch if N set), BZS (branch if Z set), BVS (branch if V set) and BCS (branch if C set) instructions simply test individual condition code bits, branching when the indicated bit is set to one. Similarly, BNR (branch if N reset), BZR (branch if Z reset), BVR (branch if V reset) and BCR (branch if C reset) branch when the indicated bits are zero.

After CMP (see Section 8.2) or CMPI (see Section 3.2), where the operands are both signed integers, BGT (branch if greater than), BGE (branch if greater than or equal), BEQ (branch if equal), BNE (branch if not equal), BLE (branch if less than or equal), and BLT (branch if less than) will branch if the first operand has the indicated relationship to the second operand. Four of these instructions involve complex tests of the condition codes, but two are merely synonyms for BZS and BZR. For example, to branch to L if r[3]>r[4], use:

        CMP     R3,R4
        BGT     L

These instructions can also be used after LOADSCC or LOADCC, where the effect is to compare the loaded signed operand with zero.

After CMP (see Section 8.2) or CMPI (see Section 3.2), where the operands are both unsigned integers, BGTU (branch if greater than unsigned), BGEU (branch if greater than or equal unsigned), BLEU (branch if less than or equal unsigned), and BLTU (branch if less than unsigned) will correctly respond to the unsigned relationship between the first and second operands. Comparison for equality is, of course, identical for signed and unsigned operands. Note that two of these instructions are merely synonyms for BCS and BCR.

The following instruction sequence will load a boolean into a r[3] from the condition codes:

	LIS	R3,TRUE
	BGT	.+4
	LIS	R3,FALSE

This sequence will load either TRUE or FALSE depending on the condition tested by the branch instruction. In this example, it will load r[3] with TRUE if the GT condition was true (if the first operand was greater than the second in the immediately preceeding compare instruction of two signed operands), and FALSE otherwise. See Section 3.2 for discussion of the LIS instruction.

The following sequence of instructions will load the 4 bit condition-code field into r[3] without use of privileged instructions and without changing the condition codes:

	LIS	R3,0
	BCS	.+4
	ADJUST  R3,PLUS1
	BVS	.+4
	ADJUST  R3,PLUS2
	BZS	.+4
	ADJUST  R3,PLUS4
	BNS	.+4
	ADJUST  R3,PLUS8

12.3. Branch

BR (branch) unconditionally transfers control to to the indicated destination. BR can be used whereever a program-counter-relative JUMP instruction is used, so long as the destination is one of the 256 reachable locations.

There are occasional contexts where an instruction that does absolutely nothing is required. All conditional branches do nothing if the displacement is zero, so any one of them could be used for this purpose, but BR with a displacement of zero is the preferred no-op for the Hawk. Assemblers should support NOP as a synonym for BR .+2.

Thus, the following three assembly language instructions should generate exactly the same results:

        NOP
        BR      .+2
        BR      NEXT
NEXT:

Note that BR .+2 branches to the next succeeding instruction because, during the assembly of the BR instruction, the assembly location counter . (dot) holds the address of the current instruction until assembly of that instruction is completed. The example BR NEXT uses an explicit label to do exactly the same thing.

The facts that NOP is coded 0000₁₆ and MOVE R15,R15 is coded as FFFF₁₆ and is also a no-op (see Section 2.2) may simplify development on PROM-based systems. One or the other of these no-ops should represent the raw, unprogrammed state of PROM, useful for patch areas reserved to hold later additions to the code, while the other should represent a value that can be overwritten over any existing code that needs to be deleted.