5. Short Immediate Instructions
|
5.1. Short Immediate Format
5.2. Load Immediate
| 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | |
| 1 1 0 - | dst | const | ||||||||||||||
The 2 instructions in the short immediate format are 16 bits long. The first byte of these instructions holds the opcode and destination register dst. The second byte holds an 8-bit constant const.
| 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | ||||||
| 1 1 0 1 | dst (nz) | const | LIS | dst,const | r[dst] = sx(const) | ||||||||||||||||
| 1 1 0 0 | dst (nz) | const | ORIS | dst,const | r[dst]=(r[dst]<<8)∨const | ||||||||||||||||
| LIS ORIS | NZVC unchanged | ||
LIS (load immediate short) loads the destination register r[dst] with the sign extended 8 bit constant. Thus, it can be used to load any value between -128 and +127 (see Section 1.5).
ORIS shifts the destination register r[dst] 8 places left and then puts the 8 bit unsigned constant into r[dst]:7:0, the least significant 8 bits of r[dst] (see Section 1.5).
Neither instruction alter the condition codes. LIS R0,const and ORIS R0,const are illegal; if used, they will cause instruction traps. (See Chapter 13) Assemblers should flag use of r[0] as an error.
LIS Rd,0 can be used to clear a register. Hawk assemblers should define CLR Rd as a synonym for LIS Rd,0.
| 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | ||||||
| 1 1 0 1 | dst (nz) | 0 0 0 0 0 0 0 0 | CLR | dst | r[dst] = 0 | ||||||||||||||||
An arbitrary 32-bit value can be loaded into a register using an LIL instruction (See Chapter 4) to load the most significant 24 bits of the constant followed by ORIS to load the bottom 8 bits. Hawk assemblers should provide a macro, LIW (load immediate word) so that, for example, LIW R3,X generates the following two instructions:
LIL R3, X >> 8
ORIS R3, X & #FF