Cesare Tinelli's Bio
Cesare Tinelli received a Ph.D. in Computer Science from the University of Illinois at Urbana-Champaign in 1999 and is currently a F. Wendell Miller Professor of Computer Science at the University of Iowa. His research interests include automated reasoning, formal methods, software verification, foundations of programming languages, and applications of logic in computer science.
Professor Tinelli has done influential work in automated reasoning, in particular in Satisfiability Modulo Theories (SMT), a field he helped establish through his research and service activities. His research has been funded both by governmental agencies (AFOSR, AFRL, DARPA, NASA, NSF, and ONR) and corporations (Amazon, Facebook, General Electric, Intel, Rockwell Collins, and United Technologies). His work has appeared in more than 90 refereed publications, including articles in such journals as Artificial Intelligence, Information and Computation, the Journal of the ACM, the Journal of Automated Reasoning, Formal Methods in System Design, Logical Methods in Computer Science, Theoretical Computer Science, and Theory and Practice of Logic Programming.
He is a founder and coordinator of the SMT-LIB initiative, an international effort aimed at standardizing benchmarks and I/O formats for SMT solvers. He has led the development of the award-winning Darwin theorem prover and the Kind 1 and Kind 2 model checkers. He has co-led the development of the widely used and award-winning CVC3 and CVC4 SMT solvers, and co-leads the development of their successor cvc5. He also co-leads the development of StarExec, a cross community web-based service for the comparative evaluation of logic solvers.
He received an NSF CAREER award in 2003 for a project on improving extended static checking of software by means of advanced automated reasoning techniques; a Haifa Verification Conference award in 2010 for his role in building and promoting the SMT community; and a CAV Award in 2021 for his pioneering contributions to the foundations of the theory and practice of SMT. He has been an invited speaker at conferences and workshops (including CADE, CAV, ETAPS, FroCoS, HVC, NFM, TABLEAUX and VSTTE) and has given invited lectures at numerous institutions worldwide (including UC Berkeley, CEA, CMU, ENS, EPFL, IMDEA, Inria, MIT, MPI, MSR, NYU, Oxford U., Stanford U., and VERIMAG) and international summer schools.
He is an associate editor of the Journal of Automated Reasoning and a founder the SMT workshop series and the Midwest Verification Day series. He has served in the program committee of more than 70 automated reasoning and formal methods conferences and workshops, as well as the steering committee of CADE, ETAPS, FTP, FroCoS, IJCAR, and SMT. He was the PC chair of FroCoS'11 and a PC co-chair of TACAS'15.
He has worked extensively with researchers and developers from companies (including General Electric, Intel, Microsoft, Rockwell Collins, and United Technologies) and governmental agencies (NASA and Onera). His students and postdocs have later taken positions at such agencies, institutions and companies as AWS, Apple, CEA, Comsoft, EPFL, GE Global Research, MathWorks, NASA, OcamlPro, Oxford U., Stanford U., Two Sigma, UCSB, U. of Innsbruck, and U. of Tokyo.