Background:
Consider this circuit: It is some kind of flipflop (hence the Q label on
the output). The problem is to figure out what kind of flopflop, but
we will work this in stages:
a) Give a timing diagram showing how Q responds when the inputs change: Inputs a and b should both go through the following values:
a 00010010111100010 b 01000111101001000
Neatness counts. Use a ruler if you can't draw a straight line. Use
graph paper if you have trouble getting uniform spacing! You may want
to graph not only the inputs and outputs, but also one or more of the
intermediate values.
(0.5 points).
In the timing diagram and logic circuit to the right, the intermediate values c, d and e have been identified. because these are the outputs of nand gates, each is forced to one whenever either input is known to be zero. The first, c, is fully determined by a and b. The second, d, is one whenever a is zero. The third, e, is one whenever b is one.
Whenever c is zero, this forces Q to one. Whenever Q is one and a is one, d, is forced to zero. Whenever Q is one and b is one, e, is forced to zero. Finally, wherever c, d and e are all one, Q is zero. This completely determines Q much of the time, but not all of the time.
The final step in the analysis is to recognize that Q, d and e will hold their previous values whenever nothing else determines their values. The values determined by this final step are shown as hollow lines in the timing diagram.
b) How do you set this flipflop? (0.2 points).
A negative-going pulse on b when a is one will set it.
c) How do you reset this flipflop? (0.2 points).
A negative-going pulse on b when a is zero will reset it.
d)
What type of flipflop is it -- in terms of overall behavior.
(0.2 points).
It is a negative pulse triggered type-D latch; a is the data input and b is the control input.
e) Now consider a second closely related circuit, as shown to the right. What is it? That is, give its full descriptive name that completely describes its function. (0.4 points).
Thinking it through first: There are two stages, a master and a slave stage, with a little optimization: The control inputs to the two stages have been combined, with one inverted relative to the other. This fits the hypothesis that it is a master-slave flipflop.
Which clock edge does it trigger on? The master stage, to the left, follows the analysis above, allowing the data input through to the output when the control input is zero. The slave stage inverts this, allowing the data input through to the output when the control input is one. Therefore, the composite circuit will transfer the data input through to the output whenever the control input goes from zero to one.
In sum, this is a positive edge-triggered type D master-slave flipflop.
h) (0.5 point)
Looking at the logic diagram in Chapter 12 with the caption "The Hawk keyboard status and control register", the error flipflop is a type D edge triggered flipflop that is clocked every time there is a keypress.
So, the event that resets the error flipflop is a keypress.
Keypresses also set the error bit. The specific circumstance that causes the error bit to be reset is that the ready bit (stored in the ready flipflop) was zero at the instant the key was pressed. That is, the ready bit had been cleared by reading the previous character before the key was pressed again.
c) (0.5 point)
USE "hawk.h" USE "monitor.h" USE "exception.h" COMMON CONSTRAINT_ERROR,EXSIZE EXT APPLICATION INT MAIN ARSIZE = 4 MAIN: STORES R1,R2 LIL R1,CONSTRAINT_ERROR ; note: there is no previous handler to save LEA R3,MAINCE STORE R3,R1,EXHAND STORE R2,R1,EXAR ; handler installed ADDI R2,R2,ARSIZE LIL R1,APPLICATION JSRS R1,R1 ; call application ADDI R2,R2,-ARSIZE ; note: there is no previous handler to restore BR MAINQT MAINCE: ; note: there is no previous handler to restore ADDI R2,R2,ARSIZE LIS R3,0 LIS R4,0 LIL R1,PUTAT JSRS R1,R1 ; putat( 0, 0 ) LEA R3,CEMSG LIL R1,PUTS JSRS R1,R1 ; puts( "constraint error" ) ADDI R2,R2,-ARSIZE MAINQT: LOADS R1,R2 JUMPS R1 CEMSG: ASCII "constraint error",0There is a fair amount of code above, but it's mostly boilerplate, little thought required.
Bus Trap. Trap PC = #000001FE Trap MA = #000FFFFCThe Hawk monitor outputs the message "Bus Trap" along with the values of the TPC and TMA registers that it got from the CPU. The TPC or Trap-PC register holds the address of the instruction, either a load or store instruction, that caused the trap. The TMA or Trap-MA register holds the memory address that caused the trap, with the least significant 2 bits (the byte in word field) borrowed to explain the nature of the problem. These bits are 00 in the example quoted above, indicating that the address FFFFC referred to a word that was not implemented (neither readable nor writable). Other possibilites include trying to fetch an instruction from non-executable memory (01), trying to write to read-only memory (10) and trying to read from non-readable memory (11). Neither the 01 nor the 11 possibility make sense in the context of what we've studied to date. to read-only memory The trap handler got the values of the TMA and TPC registers from the CPU using CPUGET instructions.