# Iowa Logic Simulator library of TTL subcircuit descriptions
# These are in the form of a UNIX shell archive.  Pipe it through sh
# (the Bourne Shell) to expand the library into useful form.

# If you're not on a UNIX system, create a directory named ttl, then use
# a text editor to break this file into the separate files from which it
# was made.  Each text file is delimited by lines containing the string
# "xxxqzzqxxx" and each file should be named with the name appearing
# between the > and < marks on the line immediately before the text of
# that file.

if mkdir ttl
 then
   echo    directory ttl created.
 else
   echo    either a file or directory named ttl already exists,
   echo    or you have no write access to the current directory.
   exit
 fi

chmod go+rx ttl
cd ttl

cat > About-TTL <<\xxxqzzqxxx
              Subcircuit Descriptions in the
             Iowa Logic Specification Language
                            for
                     Typical TTL Chips

                         Version 9

                             by
                      Douglas W. Jones
                     University of Iowa
                            1988

                     jones@cs.uiowa.edu
xxxqzzqxxx

cat > Copyright-1988 <<\xxxqzzqxxx
  Copyright 1988, Douglas Jones.

    Permission is hereby granted to make copies of the circuit
    descriptions in this directory for research or personal use so
    long as this copyright notice is included with the copies.

    Neither these circuit descriptions nor any circuit descriptions
    derived from them may be sold or incorporated into a product which
    is sold without explicit permission from the copyright holder.

    No restriction is placed on the sale or distribution of products
    that depend on these circuit descriptions, so long as no part of
    the text of these descriptions is incorporated in the product.

  Warrantee:
    These circuit descriptions are distributed without any warrantee.
    I hope they faithfully model the function of the parts described
    in the TTL Data Book (Second Edition, Texas Instruments, 1981),
    but I cannot make any warrantee that they do so.  You get what you
    pay for.

xxxqzzqxxx

cat > LS00 <<\xxxqzzqxxx
circuit LS00;
-- quadruple 2-input nand gates

time    nodelay = 0 * ns;

inputs  p1, p2, p4, p5, p13, p12, p10, p9;
outputs p3, p6, p11, p8;
parts
	g1, g2, g3, g4: nand(2, 9.5 * ns);
wires
	p1 to(nodelay) g1.in(1);
	p2 to(nodelay) g1.in(2);
	g1.out to(nodelay) p3;

	p4 to(nodelay) g2.in(1);
	p5 to(nodelay) g2.in(2);
	g2.out to(nodelay) p6;

	p13 to(nodelay) g3.in(1);
	p12 to(nodelay) g3.in(2);
	g3.out to(nodelay) p11;

	p10 to(nodelay) g4.in(1);
	p9 to(nodelay) g4.in(2);
	g4.out to(nodelay) p8;
end.
xxxqzzqxxx
cat > LS02 <<\xxxqzzqxxx
circuit LS02;
-- quadruple 2-input nor gates

time    nodelay = 0 * ns;

inputs  p2, p3, p5, p6, p12, p11, p9, p8;
outputs p1, p4, p13, p10;
parts
	g1, g2, g3, g4: nor(2, 10 * ns);
wires
	p2 to(nodelay) g1.in(1);
	p3 to(nodelay) g1.in(2);
	g1.out to(nodelay) p1;

	p5 to(nodelay) g2.in(1);
	p6 to(nodelay) g2.in(2);
	g2.out to(nodelay) p4;

	p12 to(nodelay) g3.in(1);
	p11 to(nodelay) g3.in(2);
	g3.out to(nodelay) p13;

	p9 to(nodelay) g4.in(1);
	p8 to(nodelay) g4.in(2);
	g4.out to(nodelay) p10;
end.
xxxqzzqxxx
cat > LS04 <<\xxxqzzqxxx
circuit LS04;
-- hex inverters

time    nodelay = 0 * ns;

inputs  p1, p3, p5, p13, p11, p9;
outputs p2, p4, p6, p12, p10, p8;
parts
	g1, g2, g3, g4, g5, g6: not(9.5 * ns);
wires
	p1 to(nodelay) g1.in;
	g1.out to(nodelay) p2;

	p3 to(nodelay) g2.in;
	g2.out to(nodelay) p4;

	p5 to(nodelay) g3.in;
	g3.out to(nodelay) p6;

	p13 to(nodelay) g4.in;
	g4.out to(nodelay) p12;

	p11 to(nodelay) g5.in;
	g5.out to(nodelay) p10;

	p9 to(nodelay) g6.in;
	g6.out to(nodelay) p8;
end.
xxxqzzqxxx
cat > LS08 <<\xxxqzzqxxx
circuit LS08;
-- quadruple 2-input and gates

time    nodelay = 0 * ns;

inputs p1, p2, p4, p5, p13, p12, p10, p9;
outputs p3, p6, p11, p8;
parts
	g1, g2, g3, g4: and(2, 9 * ns);
wires
	p1 to(nodelay) g1.in(1);
	p2 to(nodelay) g1.in(2);
	g1.out to(nodelay) p3;

	p4 to(nodelay) g2.in(1);
	p5 to(nodelay) g2.in(2);
	g2.out to(nodelay) p6;

	p13 to(nodelay) g3.in(1);
	p12 to(nodelay) g3.in(2);
	g3.out to(nodelay) p11;

	p10 to(nodelay) g4.in(1);
	p9 to(nodelay) g4.in(2);
	g4.out to(nodelay) p8;
end.
xxxqzzqxxx
cat > LS10 <<\xxxqzzqxxx
circuit LS10;
-- triple 3-input nand gates

time    nodelay = 0 * ns;

inputs  p1, p2, p13, p3, p4, p5, p11, p10, p9;
outputs p12, p6, p8;
parts
	g1, g2, g3: nand(3, 9.5 * ns);
wires
	p1 to(nodelay) g1.in(1);
	p2 to(nodelay) g1.in(2);
	p13 to(nodelay) g1.in(3);
	g1.out to(nodelay) p12;

	p3 to(nodelay) g2.in(1);
	p4 to(nodelay) g2.in(2);
	p5 to(nodelay) g2.in(3);
	g2.out to(nodelay) p6;

	p11 to(nodelay) g3.in(1);
	p10 to(nodelay) g3.in(2);
	p9 to(nodelay) g3.in(3);
	g3.out to(nodelay) p8;
end.
xxxqzzqxxx
cat > LS109A <<\xxxqzzqxxx
circuit LS109A;
-- dual J-Kbar with clear and preset

time    nodelay = 0 * ns;

    circuit flop;
    inputs  pre, clr, clk, j, kbar;
    outputs q, qbar;
    parts
	    g1, g2: and(4, 2 * ns);
	    g3: nor(2, 2 * ns);
	    g4, g5, g6: nand(3, 3 * ns);
	    g7, g8: nand(3, 10 * ns);
    wires
	    pre to(nodelay) g4.in(2), g7.in(1);
	    clk to(nodelay) g5.in(2), g6.in(2);
	    j to(nodelay) g1.in(1);
	    kbar to(nodelay) g2.in(2);
	    clr to(nodelay) g1.in(3), g2.in(3), g5.in(3), g8.in(3);
	    g1.out to(nodelay) g3.in(1);
	    g2.out to(nodelay) g3.in(2);
	    g3.out to(nodelay) g4.in(3), g6.in(3);
	    g4.out to(nodelay) g5.in(1);
	    g5.out to(nodelay) g4.in(1), g6.in(1), g7.in(2);
	    g6.out to(nodelay) g1.in(4), g2.in(4), g8.in(2);
	    g7.out to(nodelay) g2.in(1), g8.in(1), q;
	    g8.out to(nodelay) g1.in(2), g7.in(3), qbar;
    end;

inputs  p1, p2, p3, p4, p5, p15, p14, p13, p12, p11;
outputs p6, p7, p10, p9;
parts
	g1, g2: flop;
wires
	p1 to(nodelay) g1.clr;
	p2 to(nodelay) g1.j;
	p3 to(nodelay) g1.kbar;
	p4 to(nodelay) g1.clk;
	p5 to(nodelay) g1.pre;
	g1.q to(nodelay) p6;
	g1.qbar to(nodelay) p7;

	p15 to(nodelay) g2.clr;
	p14 to(nodelay) g2.j;
	p13 to(nodelay) g2.kbar;
	p12 to(nodelay) g2.clk;
	p11 to(nodelay) g2.pre;
	g2.q to(nodelay) p10;
	g2.qbar to(nodelay) p9;
end.
xxxqzzqxxx
cat > LS11 <<\xxxqzzqxxx
circuit LS11;
-- triple 3-input nand gates

time    nodelay = 0 * ns;

inputs  p1, p2, p13, p3, p4, p5, p11, p10, p9;
outputs p12, p6, p8;
parts
	g1, g2, g3: and(3, 9 * ns);
wires
	p1 to(nodelay) g1.in(1);
	p2 to(nodelay) g1.in(2);
	p13 to(nodelay) g1.in(3);
	g1.out to(nodelay) p12;

	p3 to(nodelay) g2.in(1);
	p4 to(nodelay) g2.in(2);
	p5 to(nodelay) g2.in(3);
	g2.out to(nodelay) p6;

	p11 to(nodelay) g3.in(1);
	p10 to(nodelay) g3.in(2);
	p9 to(nodelay) g3.in(3);
	g3.out to(nodelay) p8;
end.
xxxqzzqxxx
cat > LS125A <<\xxxqzzqxxx
circuit LS125A;
-- quadruple bus buffer gates with three-state outputs, inverted enable

time    nodelay = 0 * ns;

inputs  p1, p2, p4, p5, p13, p12, p10, p9;
outputs p3, p6, p11, p8;
parts
	g1, g2, g3, g4: tsgate(8 * ns);
	g5, g6, g7, g8: not(5 * ns);
wires
	p1 to(nodelay) g5.in;
	g5.out to(nodelay) g1.control;
	p2 to(nodelay) g1.data;
	g1.out to(nodelay) p3;

	p4 to(nodelay) g6.in;
	g6.out to(nodelay) g2.control;
	p5 to(nodelay) g2.data;
	g2.out to(nodelay) p6;

	p13 to(nodelay) g7.in;
	g7.out to(nodelay) g3.control;
	p12 to(nodelay) g3.data;
	g3.out to(nodelay) p11;

	p10 to(nodelay) g8.in;
	g8.out to(nodelay) g4.control;
	p9 to(nodelay) g4.data;
	g4.out to(nodelay) p8;
end.
xxxqzzqxxx
cat > LS139 <<\xxxqzzqxxx
circuit LS139;
-- dual 2-line to 4-line decoder/demultiplexer

time    nodelay = 0 * ns;

    circuit demux;
    inputs  a, b, g;
    outputs y0, y1, y2, y3;
    parts
	    g1, g2, g3, g4: nand(3, 9.5 * ns);
	    g5: not(9 * ns);
	    g6, g7: not(8 * ns);
	    g8, g9: not(4 * ns);
    wires
	    a to(nodelay) g6.in;
	    g6.out to(nodelay) g8.in, g1.in(1), g3.in(1);
	    g8.out to(nodelay) g2.in(1), g4.in(1);
	    b to(nodelay) g7.in;
	    g7.out to(nodelay) g9.in, g1.in(2), g2.in(2);
	    g9.out to(nodelay) g3.in(2), g4.in(2);

	    g to(nodelay) g5.in;
	    g5.out to(nodelay) g1.in(3), g2.in(3), g3.in(3), g4.in(3);
	    g1.out to(nodelay) y0;
	    g2.out to(nodelay) y1;
	    g3.out to(nodelay) y2;
	    g4.out to(nodelay) y3;
    end;

inputs  p1, p2, p3, p15, p14, p13;
outputs p4, p5, p6, p7, p12, p11, p10, p9;
parts
	g1, g2: demux;
wires
	p1 to(nodelay) g1.g;
	p2 to(nodelay) g1.a;
	p3 to(nodelay) g1.b;
	g1.y0 to(nodelay) p4;
	g1.y1 to(nodelay) p5;
	g1.y2 to(nodelay) p6;
	g1.y3 to(nodelay) p7;

	p15 to(nodelay) g2.g;
	p14 to(nodelay) g2.a;
	p13 to(nodelay) g2.b;
	g2.y0 to(nodelay) p12;
	g2.y1 to(nodelay) p11;
	g2.y2 to(nodelay) p10;
	g2.y3 to(nodelay) p9;
end.
xxxqzzqxxx
cat > LS153 <<\xxxqzzqxxx
circuit LS153;
-- dual 4-line to 1-line data selector/multiplexer with separate enables

time    nodelay = 0 * ns;

inputs  p1, p6, p5, p4, p3, p2, p14, p10, p11, p12, p13, p15;
outputs p7, p9;
parts
	g1, g2, g3, g4, g5, g6, g7, g8: and(4, 5 * ns);
	g9, g10: or(4, 9.5 * ns);
	g11, g12, g13, g14, g15, g16: not(4 * ns);
wires
	p1 to(nodelay) g11.in;
	g11.out to(nodelay) g1.in(1), g2.in(1), g3.in(1), g4.in(1);
	p15 to(nodelay) g16.in;
	g16.out to(nodelay) g5.in(1), g6.in(1), g7.in(1), g8.in(1);

	p2 to(nodelay) g12.in;
	g12.out to(nodelay) g13.in, g1.in(2), g2.in(2), g5.in(2), g6.in(2);
	g13.out to(nodelay) g3.in(2), g4.in(2), g7.in(2), g8.in(2);
	p14 to(nodelay) g14.in;
	g14.out to(nodelay) g15.in, g1.in(3), g3.in(3), g5.in(3), g7.in(3);
	g15.out to(nodelay) g2.in(3), g4.in(3), g6.in(3), g8.in(3);

	p6 to(nodelay) g1.in(4);
	p5 to(nodelay) g2.in(4);
	p4 to(nodelay) g3.in(4);
	p3 to(nodelay) g4.in(4);
	g1.out to(nodelay) g9.in(1);
	g2.out to(nodelay) g9.in(2);
	g3.out to(nodelay) g9.in(3);
	g4.out to(nodelay) g9.in(4);
	g9.out to(nodelay) p7;

	p10 to(nodelay) g5.in(4);
	p11 to(nodelay) g6.in(4);
	p12 to(nodelay) g7.in(4);
	p13 to(nodelay) g8.in(4);
	g5.out to(nodelay) g10.in(1);
	g6.out to(nodelay) g10.in(2);
	g7.out to(nodelay) g10.in(3);
	g8.out to(nodelay) g10.in(4);
	g10.out to(nodelay) p9;
end.
xxxqzzqxxx
cat > LS157 <<\xxxqzzqxxx
circuit LS157;
-- quadruple 2-line to 1-line non-inverting data selector/multiplexer

time    nodelay = 0 * ns;

inputs  p2, p3, p5, p6, p11, p10, p14, p13, p15, p1;
outputs p4, p7, p9, p12;
parts
	g1, g2, g3, g4, g5, g6, g7, g8: and(2, 4.5 * ns);
	g9, g10, g11, g12: or(2, 4.5 * ns);
        g13, g14: nor(2, 4.5 * ns);
	g15: not(3 * ns);
wires
	p1 to(nodelay) g15.in, g13.in(2);
	g15.out to(nodelay) g14.in(2);
	p15 to(nodelay) g13.in(1), g14.in(1);
	g13.out to(nodelay) g1.in(2), g3.in(2), g5.in(2), g7.in(2);
	g14.out to(nodelay) g2.in(2), g4.in(2), g6.in(2), g8.in(2);

	p2 to(nodelay) g1.in(1);
	p3 to(nodelay) g2.in(1);
	g1.out to(nodelay) g9.in(1);
	g2.out to(nodelay) g9.in(2);
	g9.out to(nodelay) p4;

	p5 to(nodelay) g3.in(1);
	p6 to(nodelay) g4.in(1);
	g3.out to(nodelay) g10.in(1);
	g4.out to(nodelay) g10.in(2);
	g10.out to(nodelay) p7;

	p11 to(nodelay) g5.in(1);
	p10 to(nodelay) g6.in(1);
	g5.out to(nodelay) g11.in(1);
	g6.out to(nodelay) g11.in(2);
	g11.out to(nodelay) p9;

	p14 to(nodelay) g7.in(1);
	p13 to(nodelay) g8.in(1);
	g7.out to(nodelay) g12.in(1);
	g8.out to(nodelay) g12.in(2);
	g12.out to(nodelay) p12;
end.
xxxqzzqxxx
cat > LS158 <<\xxxqzzqxxx
circuit LS158;
-- quadruple 2-line to 1-line inverting data selector/multiplexer

time    nodelay = 0 * ns;

inputs  p2, p3, p5, p6, p11, p10, p14, p13, p15, p1;
outputs p4, p7, p9, p12;
parts
	g1, g2, g3, g4, g5, g6, g7, g8: and(2, 4.5 * ns);
	g9, g10, g11, g12: nor(2, 4 * ns);
        g13, g14: nor(2, 4.5 * ns);
	g15: not(2 * ns);
wires
	p1 to(nodelay) g15.in, g13.in(2);
	g15.out to(nodelay) g14.in(2);
	p15 to(nodelay) g13.in(1), g14.in(1);
	g13.out to(nodelay) g1.in(2), g3.in(2), g5.in(2), g7.in(2);
	g14.out to(nodelay) g2.in(2), g4.in(2), g6.in(2), g8.in(2);

	p2 to(nodelay) g1.in(1);
	p3 to(nodelay) g2.in(1);
	g1.out to(nodelay) g9.in(1);
	g2.out to(nodelay) g9.in(2);
	g9.out to(nodelay) p4;

	p5 to(nodelay) g3.in(1);
	p6 to(nodelay) g4.in(1);
	g3.out to(nodelay) g10.in(1);
	g4.out to(nodelay) g10.in(2);
	g10.out to(nodelay) p7;

	p11 to(nodelay) g5.in(1);
	p10 to(nodelay) g6.in(1);
	g5.out to(nodelay) g11.in(1);
	g6.out to(nodelay) g11.in(2);
	g11.out to(nodelay) p9;

	p14 to(nodelay) g7.in(1);
	p13 to(nodelay) g8.in(1);
	g7.out to(nodelay) g12.in(1);
	g8.out to(nodelay) g12.in(2);
	g12.out to(nodelay) p12;
end.
xxxqzzqxxx
cat > LS174 <<\xxxqzzqxxx
circuit LS174;
-- hex D-type positive-edge-triggered flop-flops with common clock and clear

time	nodelay = 0 * ns;

    circuit dflip;
    -- borrowed from the SN7474 description in the TTL Data Book
    inputs  d, ck, clr;
    outputs q;
    parts
	    g2, g3, g4, g6: nand(3, 8 * ns);
	    g1, g5: nand(2, 8 * ns);
    wires
	    clr to(nodelay) g2.in(2), g6.in(2), g4.in(2);
	    ck to(nodelay) g3.in(2), g2.in(3);
	    d to(nodelay) g4.in(3);
	    g1.out to(nodelay) g2.in(1);
	    g2.out to(nodelay) g1.in(2), g5.in(1), g3.in(1);
	    g3.out to(nodelay) g6.in(3), g4.in(1);
	    g4.out to(nodelay) g3.in(3), g1.in(1);
	    g5.out to(nodelay) g6.in(1), q;
	    g6.out to(nodelay) g5.in(2);
    end { dflip };

inputs  p1, p3, p4, p6, p14, p13, p11, p9;
outputs p2, p5, p7, p15, p12, p10;
parts
        ff1, ff2, ff3, ff4, ff5, ff6: dflip;
wires
	{ the following gets the timing right, but not the input loading }
        p1 to(4 * ns) ff1.clr, ff2.clr, ff3.clr, ff4.clr, ff5.clr, ff6.clr;
	p9 to(nodelay) ff1.ck, ff2.ck, ff3.ck, ff4.ck, ff5.ck, ff6.ck;

	p3 to(nodelay) ff1.d;
	ff1.q to(nodelay) p2;

	p4 to(nodelay) ff2.d;
	ff2.q to(nodelay) p5;

	p6 to(nodelay) ff3.d;
	ff3.q to(nodelay) p7;

	p14 to(nodelay) ff4.d;
	ff4.q to(nodelay) p15;

	p13 to(nodelay) ff5.d;
	ff5.q to(nodelay) p12;

	p11 to(nodelay) ff6.d;
	ff6.q to(nodelay) p10;
end.
xxxqzzqxxx
cat > LS175 <<\xxxqzzqxxx
circuit LS175;
-- quad D-type positive-edge-triggered flop-flops with common clock and clear

time	nodelay = 0 * ns;

    circuit dflip;
    -- borrowed from the 7474 description in the TTL Data Book
    inputs  d, ck, clr;
    outputs q, qbar;
    parts
	    g2, g3, g4, g6: nand(3, 8 * ns);
	    g1, g5: nand(2, 8 * ns);
    wires
	    clr to(nodelay) g2.in(2), g6.in(2), g4.in(2);
	    ck to(nodelay) g3.in(2), g2.in(3);
	    d to(nodelay) g4.in(3);
	    g1.out to(nodelay) g2.in(1);
	    g2.out to(nodelay) g1.in(2), g5.in(1), g3.in(1);
	    g3.out to(nodelay) g6.in(3), g4.in(1);
	    g4.out to(nodelay) g3.in(3), g1.in(1);
	    g5.out to(nodelay) g6.in(1), q;
	    g6.out to(nodelay) g5.in(2), qbar;
    end { dflip };

inputs  p1, p4, p5, p13, p12, p9;
outputs p2, p3, p6, p7, p15, p14, p11, p10;
parts
        ff1, ff2, ff3, ff4: dflip;
wires
	{ the following gets the timing right, but not the input loading }
        p1 to(4 * ns) ff1.clr, ff2.clr, ff3.clr, ff4.clr;
	p9 to(nodelay) ff1.ck, ff2.ck, ff3.ck, ff4.ck;

	p4 to(nodelay) ff1.d;
	ff1.q to(nodelay) p2;
	ff1.qbar to(nodelay) p3;

	p5 to(nodelay) ff2.d;
	ff2.q to(nodelay) p7;
	ff2.qbar to(nodelay) p6;

	p13 to(nodelay) ff3.d;
	ff3.q to(nodelay) p15;
	ff3.qbar to(nodelay) p14;

	p12 to(nodelay) ff4.d;
	ff4.q to(nodelay) p10;
	ff4.qbar to(nodelay) p11;
end.
xxxqzzqxxx
cat > LS183 <<\xxxqzzqxxx
circuit LS183;
-- dual full adders

time	nodelay = 0 * ns;

    circuit add;
    inputs  a, b, cin;
    outputs s, cout;
    parts
	    g1, g2, g3: not(4 * ns);
	    g4, g5, g6: and(2, 4 * ns);
	    g7, g8, g9, g10: and(3, 4 * ns);
	    g11: nor(3, 5 * ns);
	    g12: nor(4, 5 * ns);
    wires
	    cin to(nodelay) g1.in, g7.in(1), g10.in(1);
	    g1.out to(nodelay) g4.in(1), g6.in(1), g8.in(1), g9.in(1);

	    b to(nodelay) g2.in, g8.in(2), g10.in(2);
	    g2.out to(nodelay) g4.in(2), g5.in(1), g7.in(2), g9.in(2);

	    a to(nodelay) g3.in, g7.in(3), g8.in(3);
	    g3.out to(nodelay) g5.in(2), g6.in(2), g9.in(3), g10.in(3);

	    g4.out to(nodelay) g11.in(1);
	    g5.out to(nodelay) g11.in(2);
	    g6.out to(nodelay) g11.in(3);
	    g11.out to(nodelay) cout;

	    g7.out to(nodelay) g12.in(1);
	    g8.out to(nodelay) g12.in(2);
	    g9.out to(nodelay) g12.in(3);
	    g10.out to(nodelay) g12.in(4);
	    g12.out to(nodelay) s;
    end;

inputs	p1, p3, p4, p13, p12, p11;
outputs p5, p6, p10, p8;
parts
	g1, g2: add;
wires
	p1 to(nodelay) g1.a;
	p3 to(nodelay) g1.b;
	p4 to(nodelay) g1.cin;
	g1.cout to(nodelay) p5;
	g1.s to(nodelay) p6;

	p13 to(nodelay) g2.a;
	p12 to(nodelay) g2.b;
	p11 to(nodelay) g2.cin;
	g2.cout to(nodelay) p10;
	g2.s to(nodelay) p8;
end.
xxxqzzqxxx
cat > LS20 <<\xxxqzzqxxx
circuit LS20;
-- dual 4-input nand gates

time    nodelay = 0 * ns;

inputs  p1, p2, p4, p5, p13, p12, p10, p9;
outputs p6, p8;
parts
	g1, g2: nand(4, 9.5 * ns);
wires
	p1 to(nodelay) g1.in(1);
	p2 to(nodelay) g1.in(2);
	p4 to(nodelay) g1.in(3);
	p5 to(nodelay) g1.in(4);
	g1.out to(nodelay) p6;

	p13 to(nodelay) g2.in(1);
	p12 to(nodelay) g2.in(2);
	p10 to(nodelay) g2.in(3);
	p9 to(nodelay) g2.in(4);
	g2.out to(nodelay) p8;
end.
xxxqzzqxxx
cat > LS21 <<\xxxqzzqxxx
circuit LS21;
-- dual 4-input and gates

time    nodelay = 0 * ns;

inputs  p1, p2, p4, p5, p13, p12, p10, p9;
outputs p6, p8;
parts
	g1, g2: and(4, 9 * ns);
wires
	p1 to(nodelay) g1.in(1);
	p2 to(nodelay) g1.in(2);
	p4 to(nodelay) g1.in(3);
	p5 to(nodelay) g1.in(4);
	g1.out to(nodelay) p6;

	p13 to(nodelay) g2.in(1);
	p12 to(nodelay) g2.in(2);
	p10 to(nodelay) g2.in(3);
	p9 to(nodelay) g2.in(4);
	g2.out to(nodelay) p8;
end.
xxxqzzqxxx
cat > LS240 <<\xxxqzzqxxx
circuit LS240;
-- octal inverting buffers and line drivers with 3-state outputs

time	nodelay = 0 * ns;

inputs  p1, p2, p4, p6, p8, p17, p15, p13, p11, p19;
outputs p3, p5, p7, p9, p18, p16, p14, p12;
parts
	g1, g2, g3, g4, g5, g6, g7, g8: ntsgate( 10 * ns );
	g9, g10: not( 4 * ns );
wires
	p1 to(nodelay) g9.in;
	g9.out to(nodelay) g1.control, g2.control, g3.control, g4.control;
	p19 to(nodelay) g10.in;
	g10.out to(nodelay) g5.control, g6.control, g7.control, g8.control;

	p2 to(nodelay) g1.data;
	g1.out to(nodelay) p18;

	p4 to(nodelay) g2.data;
	g2.out to(nodelay) p16;

	p6 to(nodelay) g3.data;
	g3.out to(nodelay) p14;

	p8 to(nodelay) g4.data;
	g4.out to(nodelay) p12;

	p17 to(nodelay) g5.data;
	g5.out to(nodelay) p3;

	p15 to(nodelay) g6.data;
	g6.out to(nodelay) p5;

	p13 to(nodelay) g7.data;
	g7.out to(nodelay) p7;

	p11 to(nodelay) g8.data;
	g8.out to(nodelay) p9;
end.
xxxqzzqxxx
cat > LS244 <<\xxxqzzqxxx
circuit LS244;
-- octal buffers and line drivers with 3-state outputs

time	nodelay = 0 * ns;

inputs  p1, p2, p4, p6, p8, p17, p15, p13, p11, p19;
outputs p3, p5, p7, p9, p18, p16, p14, p12;
parts
	g1, g2, g3, g4, g5, g6, g7, g8: tsgate( 12 * ns );
	g9, g10: not( 4 * ns );
wires
	p1 to(nodelay) g9.in;
	g9.out to(nodelay) g1.control, g2.control, g3.control, g4.control;
	p19 to(nodelay) g10.in;
	g10.out to(nodelay) g5.control, g6.control, g7.control, g8.control;

	p2 to(nodelay) g1.data;
	g1.out to(nodelay) p18;

	p4 to(nodelay) g2.data;
	g2.out to(nodelay) p16;

	p6 to(nodelay) g3.data;
	g3.out to(nodelay) p14;

	p8 to(nodelay) g4.data;
	g4.out to(nodelay) p12;

	p17 to(nodelay) g5.data;
	g5.out to(nodelay) p3;

	p15 to(nodelay) g6.data;
	g6.out to(nodelay) p5;

	p13 to(nodelay) g7.data;
	g7.out to(nodelay) p7;

	p11 to(nodelay) g8.data;
	g8.out to(nodelay) p9;
end.
xxxqzzqxxx
cat > LS27 <<\xxxqzzqxxx
circuit LS27;
-- triple 3-input nor gates

time    nodelay = 0 * ns;

inputs  p1, p2, p13, p3, p4, p5, p11, p10, p9;
outputs p12, p6, p8;
parts
	g1, g2, g3: nor(3, 10 * ns);
wires
	p1 to(nodelay) g1.in(1);
	p2 to(nodelay) g1.in(2);
	p13 to(nodelay) g1.in(3);
	g1.out to(nodelay) p12;

	p3 to(nodelay) g2.in(1);
	p4 to(nodelay) g2.in(2);
	p5 to(nodelay) g2.in(3);
	g2.out to(nodelay) p6;

	p11 to(nodelay) g3.in(1);
	p10 to(nodelay) g3.in(2);
	p9 to(nodelay) g3.in(3);
	g3.out to(nodelay) p8;
end.
xxxqzzqxxx
cat > LS273 <<\xxxqzzqxxx
circuit LS273;
-- octal D-type positive-edge-triggered flop-flops with common clock and clear

time	nodelay = 0 * ns;

    circuit dflip;
    -- borrowed from the 7474 description in the TTL Data Book
    inputs  d, ck, clr;
    outputs q;
    parts
	    g2, g3, g4, g6: nand(3, 8 * ns);
	    g1, g5: nand(2, 8 * ns);
    wires
	    clr to(nodelay) g2.in(2), g6.in(2), g4.in(2);
	    ck to(nodelay) g3.in(2), g2.in(3);
	    d to(nodelay) g4.in(3);
	    g1.out to(nodelay) g2.in(1);
	    g2.out to(nodelay) g1.in(2), g5.in(1), g3.in(1);
	    g3.out to(nodelay) g6.in(3), g4.in(1);
	    g4.out to(nodelay) g3.in(3), g1.in(1);
	    g5.out to(nodelay) g6.in(1), q;
	    g6.out to(nodelay) g5.in(2);
    end { dflip };

inputs  p1, p3, p4, p7, p8, p13, p14, p17, p18, p11;
outputs p2, p5, p6, p9, p12, p15, p16, p19;
parts
        ff1, ff2, ff3, ff4, ff5, ff6, ff7, ff8: dflip;
wires
	{ the following gets the timing right, but not the input loading }
        p1 to(nodelay) ff1.clr, ff2.clr, ff3.clr, ff4.clr,
		       ff5.clr, ff6.clr, ff7.clr, ff8.clr;
	p11 to(nodelay) ff1.ck, ff2.ck, ff3.ck, ff4.ck,
			ff5.ck, ff6.ck, ff7.ck, ff8.ck;

	p3 to(nodelay) ff1.d;
	ff1.q to(nodelay) p2;

	p4 to(nodelay) ff2.d;
	ff2.q to(nodelay) p5;

	p7 to(nodelay) ff3.d;
	ff3.q to(nodelay) p6;

	p8 to(nodelay) ff4.d;
	ff4.q to(nodelay) p9;

	p13 to(nodelay) ff5.d;
	ff5.q to(nodelay) p12;

	p14 to(nodelay) ff6.d;
	ff6.q to(nodelay) p15;

	p17 to(nodelay) ff7.d;
	ff7.q to(nodelay) p16;

	p18 to(nodelay) ff8.d;
	ff8.q to(nodelay) p19;
end.
xxxqzzqxxx
cat > LS30 <<\xxxqzzqxxx
circuit LS30;
-- 8-input nand gate

time    nodelay = 0 * ns;

inputs  p1, p2, p3, p4, p5, p6, p12, p11;
outputs p8;
parts
	g1: nand(8, 10.5 * ns);
wires
	p1 to(nodelay) g1.in(1);
	p2 to(nodelay) g1.in(2);
	p3 to(nodelay) g1.in(3);
	p4 to(nodelay) g1.in(4);
	p5 to(nodelay) g1.in(5);
	p6 to(nodelay) g1.in(6);
	p12 to(nodelay) g1.in(7);
	p11 to(nodelay) g1.in(8);
	g1.out to(nodelay) p8;
end.
xxxqzzqxxx
cat > LS32 <<\xxxqzzqxxx
circuit LS32;
-- quadruple 2-input or gates

time    nodelay = 0 * ns;

inputs  p1, p2, p4, p5, p13, p12, p10, p9;
outputs p3, p6, p11, p8;
parts
	g1, g2, g3, g4: or(2, 14*ns);
wires
	p1 to(nodelay) g1.in(1);
	p2 to(nodelay) g1.in(2);
	g1.out to(nodelay) p3;

	p4 to(nodelay) g2.in(1);
	p5 to(nodelay) g2.in(2);
	g2.out to(nodelay) p6;

	p13 to(nodelay) g3.in(1);
	p12 to(nodelay) g3.in(2);
	g3.out to(nodelay) p11;

	p10 to(nodelay) g4.in(1);
	p9 to(nodelay) g4.in(2);
	g4.out to(nodelay) p8;
end.
xxxqzzqxxx
cat > LS352 <<\xxxqzzqxxx
circuit LS352;
-- dual 4-line to 1-line inverting data selector/multiplexer w/ separate enables

time    nodelay = 0 * ns;

inputs  p1, p6, p5, p4, p3, p2, p14, p10, p11, p12, p13, p15;
outputs p7, p9;
parts
	g1, g2, g3, g4, g5, g6, g7, g8: and(4, 5 * ns);
	g9, g10: nor(4, 10 * ns);
	g11, g12, g13, g14, g15, g16: not(4 * ns);
wires
	p1 to(nodelay) g11.in;
	g11.out to(nodelay) g1.in(1), g2.in(1), g3.in(1), g4.in(1);
	p15 to(nodelay) g16.in;
	g16.out to(nodelay) g5.in(1), g6.in(1), g7.in(1), g8.in(1);

	p2 to(nodelay) g12.in;
	g12.out to(nodelay) g13.in, g1.in(2), g2.in(2), g5.in(2), g6.in(2);
	g13.out to(nodelay) g3.in(2), g4.in(2), g7.in(2), g8.in(2);
	p14 to(nodelay) g14.in;
	g14.out to(nodelay) g15.in, g1.in(3), g3.in(3), g5.in(3), g7.in(3);
	g15.out to(nodelay) g2.in(3), g4.in(3), g6.in(3), g8.in(3);

	p6 to(nodelay) g1.in(4);
	p5 to(nodelay) g2.in(4);
	p4 to(nodelay) g3.in(4);
	p3 to(nodelay) g4.in(4);
	g1.out to(nodelay) g9.in(1);
	g2.out to(nodelay) g9.in(2);
	g3.out to(nodelay) g9.in(3);
	g4.out to(nodelay) g9.in(4);
	g9.out to(nodelay) p7;

	p10 to(nodelay) g5.in(4);
	p11 to(nodelay) g6.in(4);
	p12 to(nodelay) g7.in(4);
	p13 to(nodelay) g8.in(4);
	g5.out to(nodelay) g10.in(1);
	g6.out to(nodelay) g10.in(2);
	g7.out to(nodelay) g10.in(3);
	g8.out to(nodelay) g10.in(4);
	g10.out to(nodelay) p9;
end.
xxxqzzqxxx
cat > LS367A <<\xxxqzzqxxx
circuit LS367A;
-- hex non-inverted 3-state buffers

time	nodelay = 0 * ns;

inputs	p1, p2, p4, p6, p15, p14, p12, p10;
outputs p3, p5, p7, p13, p11, p9;
parts
	g1, g2, g3, g4, g5, g6: tsgate(10 * ns);
	g7, g8: not(11 * ns);
wires
	p1 to(nodelay) g7.in;
	g7.out to(nodelay) g1.control, g2.control, g3.control, g6.control;

	p15 to(nodelay) g8.in;
	g8.out to(nodelay) g4.control, g5.control;

	p2 to(nodelay) g1.data;
	g1.out to(nodelay) p3;

	p4 to(nodelay) g2.data;
	g2.out to(nodelay) p5;

	p6 to(nodelay) g3.data;
	g3.out to(nodelay) p7;

	p14 to(nodelay) g4.data;
	g4.out to(nodelay) p13;

	p12 to(nodelay) g5.data;
	g5.out to(nodelay) p11;

	p10 to(nodelay) g6.data;
	g6.out to(nodelay) p9;
end.
xxxqzzqxxx
cat > LS368A <<\xxxqzzqxxx
circuit LS368A;
-- hex inverted 3-state buffers

time	nodelay = 0 * ns;

inputs	p1, p2, p4, p6, p15, p14, p12, p10;
outputs p3, p5, p7, p13, p11, p9;
parts
	g1, g2, g3, g4, g5, g6: ntsgate(11 * ns);
	g7, g8: not(11 * ns);
wires
	p1 to(nodelay) g7.in;
	g7.out to(nodelay) g1.control, g2.control, g3.control, g6.control;

	p15 to(nodelay) g8.in;
	g8.out to(nodelay) g4.control, g5.control;

	p2 to(nodelay) g1.data;
	g1.out to(nodelay) p3;

	p4 to(nodelay) g2.data;
	g2.out to(nodelay) p5;

	p6 to(nodelay) g3.data;
	g3.out to(nodelay) p7;

	p14 to(nodelay) g4.data;
	g4.out to(nodelay) p13;

	p12 to(nodelay) g5.data;
	g5.out to(nodelay) p11;

	p10 to(nodelay) g6.data;
	g6.out to(nodelay) p9;
end.
xxxqzzqxxx
cat > LS374 <<\xxxqzzqxxx
circuit LS374;
-- octal 3-state D-type positive-edge-triggered flop-flops with common clock

time	nodelay = 0 * ns;

    circuit dflip;
    inputs  d, ck, en;
    outputs q;
    parts
	    g1: latch(8 * ns);
	    g2: tsgate(8 * ns);
    wires
	    en to(nodelay) g2.control;
	    ck to(nodelay) g1.control;
	    d to(nodelay) g1.data;
	    g1.out to(nodelay) g2.data;
	    g2.out to(nodelay) q;
    end { dflip };

inputs  p1, p3, p4, p7, p8, p13, p14, p17, p18, p11;
outputs p2, p5, p6, p9, p12, p15, p16, p19;
parts
        ff1, ff2, ff3, ff4, ff5, ff6, ff7, ff8: dflip;
	g1: not(4 * ns);
wires
        p1 to(nodelay) g1.in;
        g1.out to(nodelay) ff1.en, ff2.en, ff3.en, ff4.en,
			   ff5.en, ff6.en, ff7.en, ff8.en;
	{ the following gets the timing right, but not the input loading }
	p11 to(nodelay) ff1.ck, ff2.ck, ff3.ck, ff4.ck,
			ff5.ck, ff6.ck, ff7.ck, ff8.ck;

	p3 to(nodelay) ff1.d;
	ff1.q to(nodelay) p2;

	p4 to(nodelay) ff2.d;
	ff2.q to(nodelay) p5;

	p7 to(nodelay) ff3.d;
	ff3.q to(nodelay) p6;

	p8 to(nodelay) ff4.d;
	ff4.q to(nodelay) p9;

	p13 to(nodelay) ff5.d;
	ff5.q to(nodelay) p12;

	p14 to(nodelay) ff6.d;
	ff6.q to(nodelay) p15;

	p17 to(nodelay) ff7.d;
	ff7.q to(nodelay) p16;

	p18 to(nodelay) ff8.d;
	ff8.q to(nodelay) p19;
end.
xxxqzzqxxx
cat > LS381A <<\xxxqzzqxxx
circuit LS381A;
-- arithmetic logic units with outputs for lookahead carry

time	nodelay = 0 * ns;

    circuit inselect;
    inputs  a, b, f1, f2, f3, f4, f5, f6;
    outputs x, y;
    parts
	    g1, g2: not(0.5 * ns);
	    g3, g4, g5, g6, g7, g8, g9: and(3, 0.5 * ns);
	    g10: and(2, 0.5 * ns);
	    g11, g12: nor(4, 0.5 * ns);
    wires
	    { data input routing }
	    a to(nodelay) g1.in, g3.in(2), g4.in(2), g7.in(2), g8.in(2);
	      g1.out to(nodelay) g5.in(2), g6.in(2), g9.in(2), g10.in(1);
	    b to(nodelay) g2.in, g4.in(3), g5.in(3), g8.in(3), g9.in(3);
	      g2.out to(nodelay) g3.in(3), g6.in(3), g7.in(3), g10.in(2);

	    { function select input routing }
	    f1 to(nodelay) g6.in(1);
	    f2 to(nodelay) g4.in(1);
	    f3 to(nodelay) g3.in(1), g5.in(1);
	    f4 to(nodelay) g9.in(1);
	    f5 to(nodelay) g8.in(1);
	    f6 to(nodelay) g7.in(1);

	    { output connections }
	    g3.out to(nodelay) g11.in(1);
	    g4.out to(nodelay) g11.in(2);
	    g5.out to(nodelay) g11.in(3);
	    g6.out to(nodelay) g11.in(4);
	    g11.out to(nodelay) x;
	    g7.out to(nodelay) g12.in(1);
	    g8.out to(nodelay) g12.in(2);
	    g9.out to(nodelay) g12.in(3);
	    g10.out to(nodelay) g12.in(4);
	    g12.out to(nodelay) y;
    end { inselect };

inputs	p7, p6, p5, p15, p17, p19, p1, p3, p16, p18, p2, p4;
outputs p14, p13, p12, p11, p9, p8;
parts
	s0, s1, s2, s3: inselect;

	{ function decode parts }
	g1, g2, g3, g4, g5, g6: not(5 * ns);
	g7, g8, g9: and(3, 5 * ns);
	g10, g11, g12, g13, g14, g18, g19: and(2, 5 * ns);
	g15, g16, g17: nand(3, 10 * ns);
	g20, g21: nor(3, 5 * ns);
	g22: nor(2, 5 * ns);
	g23: or(2, 5 * ns);

	{ parts to make f0 to f3 }
	g24, g25, g26, g27: equ(5 * ns);
	g28: nor(2, 5 * ns);
	g29: nor(3, 5 * ns);
	g30: nor(4, 5 * ns);
	g31: nand(2, 10 * ns);
	g33, g36, g40: and(2, 5 * ns);
	g32, g35, g39: and(3, 5 * ns);
	g34, g38: and(4, 5 * ns);
	g37: and(5, 5 * ns);

	{ parts to make p and g }
	g41: nand(4, 10 * ns);
	g42: and(4, 5 * ns);
	g43: and(3, 5 * ns);
	g44: and(2, 5 * ns);
	g45: nor(4, 5 * ns);
wires
	{ inputs to input selection logic }
	p3 to(nodelay) s0.a;    p4 to(nodelay) s0.b;
	p1 to(nodelay) s1.a;    p2 to(nodelay) s1.b;
	p19 to(nodelay) s2.a;   p18 to(nodelay) s2.b;
	p17 to(nodelay) s3.a;   p16 to(nodelay) s3.b;

	{ function select pla and matrix }
	p5 to(nodelay) g1.in;
	g1.out to(nodelay) g2.in, g8.in(3), g12.in(2), g17.in(3);
	g2.out to(nodelay) g7.in(3), g9.in(3), g10.in(2), g11.in(2),
			     g13.in(2), g15.in(3), g16.in(3), g18.in(2);

	p6 to(nodelay) g3.in;
	g3.out to(nodelay) g4.in, g7.in(2), g10.in(1), g14.in(2), g15.in(2);
	g4.out to(nodelay) g8.in(2), g9.in(2), g12.in(1), g13.in(1),
			     g16.in(2), g17.in(2), g19.in(2);

	p7 to(nodelay) g5.in;
	g5.out to(nodelay) g6.in, g7.in(1), g8.in(1), g15.in(1), g16.in(1),
			     g17.in(1), g18.in(1), g19.in(1);
	g6.out to(nodelay) g9.in(1), g11.in(1), g14.in(1);

	{ function select pla or matrix routing }
	g7.out to(nodelay) g20.in(1);
	g8.out to(nodelay) g20.in(2);
	g9.out to(nodelay) g20.in(3);

	g10.out to(nodelay) g21.in(1);
	g11.out to(nodelay) g21.in(2);
	g12.out to(nodelay) g21.in(3);

	g13.out to(nodelay) g22.in(1);
	g14.out to(nodelay) g22.in(2);

	g18.out to(nodelay) g23.in(1);
	g19.out to(nodelay) g23.in(2);

	{ function select output routing }
	g20.out to(nodelay) s0.f1, s1.f1, s2.f1, s3.f1;
	g21.out to(nodelay) s0.f2, s1.f2, s2.f2, s3.f2;
	g22.out to(nodelay) s0.f3, s1.f3, s2.f3, s3.f3;
	g15.out to(nodelay) s0.f4, s1.f4, s2.f4, s3.f4;
	g16.out to(nodelay) s0.f5, s1.f5, s2.f5, s3.f5;
	g17.out to(nodelay) s0.f6, s1.f6, s2.f6, s3.f6;
	g23.out to(nodelay) g31.in(1), g32.in(1), g33.in(1),
			      g34.in(1), g35.in(1), g36.in(1),
			      g37.in(1), g38.in(1), g39.in(3), g40.in(1);

	{ carry in distribution }
	p15 to(nodelay) g31.in(2), g32.in(2), g34.in(2), g37.in(2);

	{ routing from input selection logic to carry accounting logic }
	s0.x to(nodelay) g24.in(1), g32.in(3), g34.in(3), g37.in(3);
	s0.y to(nodelay) g33.in(2), g35.in(3), g38.in(4);
	s1.x to(nodelay) g25.in(1), g34.in(4), g35.in(2), g37.in(4), g38.in(2);
	s1.y to(nodelay) g36.in(2), g39.in(1);
	s2.x to(nodelay) g26.in(1), g37.in(5), g38.in(3), g39.in(2);
	s2.y to(nodelay) g40.in(2);
	s3.x to(nodelay) g27.in(1);

	{ routing to function outputs }
	g31.out to(nodelay) g24.in(2);
	g24.out to(nodelay) p8;

	g32.out to(nodelay) g28.in(1);
	g33.out to(nodelay) g28.in(2);
	g28.out to(nodelay) g25.in(2);
	g25.out to(nodelay) p9;

	g34.out to(nodelay) g29.in(1);
	g35.out to(nodelay) g29.in(2);
	g36.out to(nodelay) g29.in(3);
	g29.out to(nodelay) g26.in(2);
	g26.out to(nodelay) p11;

	g37.out to(nodelay) g30.in(1);
	g38.out to(nodelay) g30.in(2);
	g39.out to(nodelay) g30.in(3);
	g40.out to(nodelay) g30.in(4);
	g30.out to(nodelay) g27.in(2);
	g27.out to(nodelay) p12;

	{ wires to make p and g }
	s0.x to(nodelay) g41.in(1);
	s1.x to(nodelay) g41.in(2), g42.in(1);
	s2.x to(nodelay) g41.in(3), g42.in(2), g43.in(1);
	s3.x to(nodelay) g41.in(4), g42.in(3), g43.in(2), g44.in(1);

	s0.y to(nodelay) g42.in(4);
	s1.y to(nodelay) g43.in(3);
	s2.y to(nodelay) g44.in(2);
	s3.y to(5 * ns) g45.in(4);

	g41.out to(nodelay) p14;

	g42.out to(nodelay) g45.in(1);
	g43.out to(nodelay) g45.in(2);
	g44.out to(nodelay) g45.in(3);
	g45.out to(nodelay) p13;
end.
xxxqzzqxxx
cat > LS382 <<\xxxqzzqxxx
circuit LS382;
-- arithmetic logic units with ripple carry output

time	nodelay = 0 * ns;

    circuit inselect;
    inputs  a, b, f1, f2, f3, f4, f5, f6;
    outputs x, y;
    parts
	    g1, g2: not(0.5 * ns);
	    g3, g4, g5, g6, g7, g8, g9: and(3, 0.5 * ns);
	    g10: and(2, 0.5 * ns);
	    g11, g12: nor(4, 0.5 * ns);
    wires
	    { data input routing }
	    a to(nodelay) g1.in, g3.in(2), g4.in(2), g7.in(2), g8.in(2);
	      g1.out to(nodelay) g5.in(2), g6.in(2), g9.in(2), g10.in(1);
	    b to(nodelay) g2.in, g4.in(3), g5.in(3), g8.in(3), g9.in(3);
	      g2.out to(nodelay) g3.in(3), g6.in(3), g7.in(3), g10.in(2);

	    { function select input routing }
	    f1 to(nodelay) g6.in(1);
	    f2 to(nodelay) g4.in(1);
	    f3 to(nodelay) g3.in(1), g5.in(1);
	    f4 to(nodelay) g9.in(1);
	    f5 to(nodelay) g8.in(1);
	    f6 to(nodelay) g7.in(1);

	    { output connections }
	    g3.out to(nodelay) g11.in(1);
	    g4.out to(nodelay) g11.in(2);
	    g5.out to(nodelay) g11.in(3);
	    g6.out to(nodelay) g11.in(4);
	    g11.out to(nodelay) x;
	    g7.out to(nodelay) g12.in(1);
	    g8.out to(nodelay) g12.in(2);
	    g9.out to(nodelay) g12.in(3);
	    g10.out to(nodelay) g12.in(4);
	    g12.out to(nodelay) y;
    end { inselect };

inputs	p7, p6, p5, p15, p17, p19, p1, p3, p16, p18, p2, p4;
outputs p14, p13, p12, p11, p9, p8;
parts
	s0, s1, s2, s3: inselect;

	{ function decode parts }
	g1, g2, g3, g4, g5, g6: not(5 * ns);
	g7, g8, g9: and(3, 5 * ns);
	g10, g11, g12, g13, g14, g18, g19: and(2, 5 * ns);
	g15, g16, g17: nand(3, 10 * ns);
	g20, g21: nor(3, 5 * ns);
	g22: nor(2, 5 * ns);
	g23: or(2, 5 * ns);

	{ parts to make f0 to f3 }
	g24, g25, g26, g27: equ(5 * ns);
	g28: nor(2, 5 * ns);
	g29: nor(3, 5 * ns);
	g30: nor(4, 5 * ns);
	g31: nand(2, 10 * ns);
	g33, g36, g40: and(2, 5 * ns);
	g32, g35, g39: and(3, 5 * ns);
	g34, g38: and(4, 5 * ns);
	g37: and(5, 5 * ns);

	{ carry and overflow detection parts }
	g41: and(5, 5 * ns);
	g42: and(4, 5 * ns);
	g43: and(3, 5 * ns);
	g44: and(2, 5 * ns);
	g45: nor(5, 5 * ns);
	g46: xor(5 * ns);
	g47: not(5 * ns);
wires
	{ inputs to input selection logic }
	p3 to(nodelay) s0.a;    p4 to(nodelay) s0.b;
	p1 to(nodelay) s1.a;    p2 to(nodelay) s1.b;
	p19 to(nodelay) s2.a;   p18 to(nodelay) s2.b;
	p17 to(nodelay) s3.a;   p16 to(nodelay) s3.b;

	{ function select pla and matrix }
	p5 to(nodelay) g1.in;
	g1.out to(nodelay) g2.in, g8.in(3), g12.in(2), g17.in(3);
	g2.out to(nodelay) g7.in(3), g9.in(3), g10.in(2), g11.in(2),
			     g13.in(2), g15.in(3), g16.in(3), g18.in(2);

	p6 to(nodelay) g3.in;
	g3.out to(nodelay) g4.in, g7.in(2), g10.in(1), g14.in(2), g15.in(2);
	g4.out to(nodelay) g8.in(2), g9.in(2), g12.in(1), g13.in(1),
			     g16.in(2), g17.in(2), g19.in(2);

	p7 to(nodelay) g5.in;
	g5.out to(nodelay) g6.in, g7.in(1), g8.in(1), g15.in(1), g16.in(1),
			     g17.in(1), g18.in(1), g19.in(1);
	g6.out to(nodelay) g9.in(1), g11.in(1), g14.in(1);

	{ function select pla or matrix routing }
	g7.out to(nodelay) g20.in(1);
	g8.out to(nodelay) g20.in(2);
	g9.out to(nodelay) g20.in(3);

	g10.out to(nodelay) g21.in(1);
	g11.out to(nodelay) g21.in(2);
	g12.out to(nodelay) g21.in(3);

	g13.out to(nodelay) g22.in(1);
	g14.out to(nodelay) g22.in(2);

	g18.out to(nodelay) g23.in(1);
	g19.out to(nodelay) g23.in(2);

	{ function select output routing }
	g20.out to(nodelay) s0.f1, s1.f1, s2.f1, s3.f1;
	g21.out to(nodelay) s0.f2, s1.f2, s2.f2, s3.f2;
	g22.out to(nodelay) s0.f3, s1.f3, s2.f3, s3.f3;
	g15.out to(nodelay) s0.f4, s1.f4, s2.f4, s3.f4;
	g16.out to(nodelay) s0.f5, s1.f5, s2.f5, s3.f5;
	g17.out to(nodelay) s0.f6, s1.f6, s2.f6, s3.f6;
	g23.out to(nodelay) g31.in(1), g32.in(1), g33.in(1),
			      g34.in(1), g35.in(1), g36.in(1),
			      g37.in(1), g38.in(1), g39.in(3), g40.in(1);

	{ carry in distribution }
	p15 to(nodelay) g31.in(2), g32.in(2), g34.in(2), g37.in(2);

	{ routing from input selection logic to carry accounting logic }
	s0.x to(nodelay) g24.in(1), g32.in(3), g34.in(3), g37.in(3);
	s0.y to(nodelay) g33.in(2), g35.in(3), g38.in(4);
	s1.x to(nodelay) g25.in(1), g34.in(4), g35.in(2), g37.in(4), g38.in(2);
	s1.y to(nodelay) g36.in(2), g39.in(1);
	s2.x to(nodelay) g26.in(1), g37.in(5), g38.in(3), g39.in(2);
	s2.y to(nodelay) g40.in(2);
	s3.x to(nodelay) g27.in(1);

	{ routing to function outputs }
	g31.out to(nodelay) g24.in(2);
	g24.out to(nodelay) p8;

	g32.out to(nodelay) g28.in(1);
	g33.out to(nodelay) g28.in(2);
	g28.out to(nodelay) g25.in(2);
	g25.out to(nodelay) p9;

	g34.out to(nodelay) g29.in(1);
	g35.out to(nodelay) g29.in(2);
	g36.out to(nodelay) g29.in(3);
	g29.out to(nodelay) g26.in(2);
	g26.out to(nodelay) p11;

	g37.out to(nodelay) g30.in(1);
	g38.out to(nodelay) g30.in(2);
	g39.out to(nodelay) g30.in(3);
	g40.out to(nodelay) g30.in(4);
	g30.out to(nodelay) g27.in(2);
	g27.out to(nodelay) p12;

	{ carry and overflow generation }
	p15 to(nodelay) g41.in(1);

	s0.x to(nodelay) g41.in(2);
	s1.x to(nodelay) g41.in(3), g42.in(1);
	s2.x to(nodelay) g41.in(4), g42.in(2), g43.in(1);
	s3.x to(nodelay) g41.in(5), g42.in(3), g43.in(2), g44.in(1);

	s0.y to(nodelay) g42.in(4);
	s1.y to(nodelay) g43.in(3);
	s2.y to(nodelay) g44.in(2);
	s3.y to(5 * ns) g45.in(5);

	g41.out to(nodelay) g45.in(1);
	g42.out to(nodelay) g45.in(2);
	g43.out to(nodelay) g45.in(3);
	g44.out to(nodelay) g45.in(4);

	g45.out to(nodelay) g46.in(2), g47.in;
	g47.out to(nodelay) p14;

	g30.out to(nodelay) g46.in(1);
	g46.out to(nodelay) p13;
end.
xxxqzzqxxx
cat > LS42 <<\xxxqzzqxxx
circuit LS42;
-- BCD to decimal decoder

time    nodelay = 0 * ns;

inputs  p15, p14, p13, p12;
outputs p1, p2, p3, p4, p5, p6, p7, p9, p10, p11;
parts
	nota, notb, notc, notd: not(5 * ns);
	a, b, c, d: not(5 * ns);
	g0, g1, g2, g3, g4, g5, g6, g7, g8, g9: nand(4, 10 * ns);
wires
	p15 to(nodelay) nota.in;
	nota.out to(nodelay) a.in;
	p14 to(nodelay) notb.in;
	notb.out to(nodelay) b.in;
	p13 to(nodelay) notc.in;
	notc.out to(nodelay) c.in;
	p12 to(nodelay) notd.in;
	notd.out to(nodelay) d.in;

	a.out to(nodelay) g1.in(1), g3.in(1), g5.in(1), g7.in(1), g9.in(1);
	nota.out to(nodelay) g0.in(1), g2.in(1), g4.in(1), g6.in(1), g8.in(1);

	b.out to(nodelay) g2.in(2), g3.in(2), g6.in(2), g7.in(2); 
	notb.out to(nodelay) g0.in(2), g1.in(2), g4.in(2), g5.in(2),
			     g8.in(2), g9.in(2); 

        c.out to(nodelay) g4.in(3), g5.in(3), g6.in(3), g7.in(3);
        notc.out to(nodelay) g0.in(3), g1.in(3), g2.in(3), g3.in(3),
			     g8.in(3), g9.in(3);

        d.out to(nodelay) g8.in(4), g9.in(4);
        notd.out to(nodelay) g0.in(4), g1.in(4), g2.in(4), g3.in(4),
			     g4.in(4), g5.in(4), g6.in(4), g7.in(4);

	g0.out to(nodelay) p1;
	g1.out to(nodelay) p2;
	g2.out to(nodelay) p3;
	g3.out to(nodelay) p4;
	g4.out to(nodelay) p5;
	g5.out to(nodelay) p6;
	g6.out to(nodelay) p7;
	g7.out to(nodelay) p9;
	g8.out to(nodelay) p10;
	g9.out to(nodelay) p11;
end.
xxxqzzqxxx
cat > LS74A <<\xxxqzzqxxx
circuit LS74A;
-- dual D-type positive-edge-triggered flop-flops with preset and clear

time	nodelay = 0 * ns;

    circuit dflip;
    inputs  d, ck, clr, pr;
    outputs q, qbar;
    parts
	    g1, g2, g3, g4, g5, g6: nand(3, 8 * ns);
    wires
	    pr to(nodelay) g1.in(1), g5.in(1);
	    clr to(nodelay) g2.in(2), g6.in(2), g4.in(2);
	    ck to(nodelay) g3.in(2), g2.in(3);
	    d to(nodelay) g4.in(3);
	    g1.out to(nodelay) g2.in(1);
	    g2.out to(nodelay) g1.in(3), g5.in(2), g3.in(1);
	    g3.out to(nodelay) g6.in(3), g4.in(1);
	    g4.out to(nodelay) g3.in(3), g1.in(2);
	    g5.out to(nodelay) g6.in(1), q;
	    g6.out to(nodelay) g5.in(3), qbar;
    end { dflip };

inputs  p1, p2, p3, p4, p13, p12, p11, p10;
outputs p5, p6, p9, p8;
parts
        ff1, ff2: dflip;
wires
        p1 to(nodelay) ff1.clr;
	p2 to(nodelay) ff1.d;
	p3 to(nodelay) ff1.ck;
	p4 to(nodelay) ff1.pr;
	ff1.q to(nodelay) p5;
	ff1.qbar to(nodelay) p6;

	p13 to(nodelay) ff2.clr;
	p12 to(nodelay) ff2.d;
	p11 to(nodelay) ff2.ck;
	p10 to(nodelay) ff2.pr;
	ff2.q to(nodelay) p9;
	ff2.qbar to(nodelay) p8;
end.
xxxqzzqxxx
cat > LS85 <<\xxxqzzqxxx
circuit LS85;
-- 4-bit magnitude comparitor

time	ndly = 0 * ns;

inputs  p15, p13, p12, p10, p1, p14, p11, p9, p2, p3, p4;
outputs p5, p6, p7;
parts
	g1, g2, g3, g4: nand(2, 2 * ns);
	g5, g6, g7, g8, g9, g10, g11, g12: and(2, 1.5 * ns);
	g13, g14, g15, g16: nor(2, 1.5 * ns);
	g17, g28: nand(2, 3 * ns);
	g18, g27: nand(3, 3 * ns);
	g19, g26: nand(4, 3 * ns);
	g20, g21, g22, g23, g24, g25: nand(5, 3 * ns);
	g29, g31: and(6, 3 * ns);
	g30: and(5, 7 * ns);
wires
	p15 to(ndly) g1.in(1), g5.in(1), g28.in(2);
	p1 to(ndly) g1.in(2), g17.in(1), g6.in(2);
	p13 to(ndly) g2.in(1), g7.in(1), g27.in(3);
	p14 to(ndly) g2.in(2), g18.in(1), g8.in(2);
	p12 to(ndly) g3.in(1), g9.in(1), g26.in(4);
	p11 to(ndly) g3.in(2), g19.in(1), g10.in(2);
	p10 to(ndly) g4.in(1), g11.in(1), g25.in(5);
	p9 to(ndly) g4.in(2), g12.in(2), g20.in(1);

	p2 to(ndly) g21.in(5);
	p4 to(ndly) g24.in(1);
	p3 to(ndly) g30.in(3), g22.in(5), g23.in(1);

	g1.out to(ndly) g17.in(2), g5.in(2), g6.in(1), g28.in(1);
	g2.out to(ndly) g18.in(2), g7.in(2), g8.in(1), g27.in(2);
	g3.out to(ndly) g19.in(2), g9.in(2), g10.in(1), g26.in(3);
	g4.out to(ndly) g20.in(2), g11.in(2), g12.in(1), g25.in(4);

	g5.out to(ndly) g13.in(1);
	g6.out to(ndly) g13.in(2);
	g7.out to(ndly) g14.in(1);
	g8.out to(ndly) g14.in(2);
	g9.out to(ndly) g15.in(1);
	g10.out to(ndly) g15.in(2);
	g11.out to(ndly) g16.in(1);
	g12.out to(ndly) g16.in(2);

	g13.out to(ndly) g18.in(3), g19.in(3), g20.in(3), g21.in(1), g22.in(1),
			 g23.in(5), g24.in(5), g25.in(3), g26.in(2), g27.in(1),
			 g30.in(1);
	g14.out to(ndly) g19.in(4), g20.in(4), g21.in(2), g22.in(2),
			 g23.in(4), g24.in(3), g25.in(2), g26.in(1),
			 g30.in(2);
	g15.out to(ndly) g20.in(5), g21.in(3), g22.in(3),
			 g23.in(3), g24.in(4), g25.in(1),
			 g30.in(4);
	g16.out to(ndly) g21.in(4), g22.in(4), g23.in(2), g24.in(2),
			 g30.in(5);

	g17.out to(ndly) g29.in(1);
	g18.out to(ndly) g29.in(2);
	g19.out to(ndly) g29.in(3);
	g20.out to(ndly) g29.in(4);
	g21.out to(ndly) g29.in(5);
	g22.out to(ndly) g29.in(6);

	g23.out to(ndly) g31.in(1);
	g24.out to(ndly) g31.in(2);
	g25.out to(ndly) g31.in(3);
	g26.out to(ndly) g31.in(4);
	g27.out to(ndly) g31.in(5);
	g28.out to(ndly) g31.in(6);

	g29.out to(ndly) p5;
	g30.out to(ndly) p6;
	g31.out to(ndly) p7;
end.
xxxqzzqxxx
cat > LS86 <<\xxxqzzqxxx
circuit LS86;
-- quadruple exclusive or gates

time    nodelay = 0 * ns;

inputs  p1, p2, p4, p5, p13, p12, p10, p9;
outputs p3, p6, p11, p8;
parts
	g1, g2, g3, g4: xor(10 * ns);
wires
	p1 to(nodelay) g1.in(1);
	p2 to(nodelay) g1.in(2);
	g1.out to(nodelay) p3;

	p4 to(nodelay) g2.in(1);
	p5 to(nodelay) g2.in(2);
	g2.out to(nodelay) p6;

	p13 to(nodelay) g3.in(1);
	p12 to(nodelay) g3.in(2);
	g3.out to(nodelay) p11;

	p10 to(nodelay) g4.in(1);
	p9 to(nodelay) g4.in(2);
	g4.out to(nodelay) p8;
end.
xxxqzzqxxx
cat > S133 <<\xxxqzzqxxx
circuit S133;
-- 13 input nand gate

time    nodelay = 0 * ns;

inputs  p1, p2, p3, p4, p5, p6, p7, p15, p14, p13, p12, p11, p10;
outputs p9;
parts
	g1: nand(13, 6 * ns);
wires
	p1 to(nodelay) g1.in(1);
	p2 to(nodelay) g1.in(2);
	p3 to(nodelay) g1.in(3);
	p4 to(nodelay) g1.in(4);
	p5 to(nodelay) g1.in(5);
	p6 to(nodelay) g1.in(6);
	p7 to(nodelay) g1.in(7);
	p15 to(nodelay) g1.in(8);
	p14 to(nodelay) g1.in(9);
	p13 to(nodelay) g1.in(10);
	p12 to(nodelay) g1.in(11);
	p11 to(nodelay) g1.in(12);
	p10 to(nodelay) g1.in(13);
	g1.out to(nodelay) p9;
end.
xxxqzzqxxx
cat > S182 <<\xxxqzzqxxx
circuit S182;
-- Look-ahead carry generators

time	nodelay = 0 * ns;

inputs  p6, p5, p15, p14, p2, p1, p4, p3, p13;
outputs p7, p10, p9, p11, p12;
parts
	g0: not(2 * ns);
	g1: or(4, 5.5 * ns);
	g2, g3, g6, g7: and(4, 2 * ns);
	g4, g8, g10, g11: and(3, 2 * ns);
	g5, g9, g12, g13, g14: and(2, 2 * ns);
	g15: or(4, 4 * ns);
	g16: nor(4, 2.5 * ns);
	g17: nor(3, 2.5 * ns);
	g18: nor(2, 2.5 * ns);
wires
	p6 to(nodelay) g1.in(1), g5.in(1);
	p5 to(nodelay) g2.in(1), g3.in(2), g4.in(2), g5.in(2);

	p15 to(nodelay) g1.in(2), g4.in(1), g9.in(1);
	p14 to(nodelay) g2.in(2), g3.in(3), g4.in(3),
			g6.in(1), g7.in(2), g8.in(2), g9.in(2);

	p2 to(nodelay) g1.in(3), g3.in(1), g8.in(1), g12.in(1);
	p1 to(nodelay) g2.in(3), g3.in(4),
		       g6.in(2), g7.in(3), g8.in(3),
		       g10.in(1), g11.in(2), g12.in(2);

	p4 to(nodelay) g1.in(4), g7.in(1), g11.in(1), g14.in(1);
	p3 to(nodelay) g2.in(4),
		       g6.in(3), g7.in(4),
		       g10.in(2), g11.in(3),
		       g13.in(1), g14.in(2);

	p13 to(nodelay) g0.in;
	g0.out to(nodelay) g6.in(4), g10.in(3), g13.in(2);

	g1.out to(nodelay) p7;

	g2.out to(nodelay) g15.in(1);
	g3.out to(nodelay) g15.in(2);
	g4.out to(nodelay) g15.in(3);
	g5.out to(nodelay) g15.in(4);
	g15.out to(nodelay) p10;

	g6.out to(nodelay) g16.in(1);
	g7.out to(nodelay) g16.in(2);
	g8.out to(nodelay) g16.in(3);
	g9.out to(nodelay) g16.in(4);
	g16.out to(nodelay) p9;

	g10.out to(nodelay) g17.in(1);
	g11.out to(nodelay) g17.in(2);
	g12.out to(nodelay) g17.in(3);
	g17.out to(nodelay) p11;

	g13.out to(nodelay) g18.in(1);
	g14.out to(nodelay) g18.in(2);
	g18.out to(nodelay) p12;
end.
xxxqzzqxxx

chmod -wx *
chmod +r *
cd ..
chmod -w ttl

echo  Done!  See files named ttl/About-TTL and ttl/Copyright-1988
echo  Note:  as created, directory ttl and all files in it are
echo  read-only and readable by the public.