# Iowa Logic Specification Language models of register-transfer level
# components.  Pipe it through sh (the Bourne Shell) to expand the
# library into useful form.

# If you're not on a UNIX system, create a directory named demo, then use
# a text editor to break this file into the separate files from which it
# was made.  Each text file is delimited by lines containing the string
# "xxxqzzqxxx" and each file should be named with the name appearing
# between the > and < marks on the line immediately before the text of
# that file.

if mkdir rtl
 then
   echo    directory rtl created.
 else
   echo    either a file or directory named rtl already exists,
   echo    or you have no write access to the current directory.
   exit
 fi

chmod go+rx rtl
cd rtl

cat > README <<\xxxqzzqxxx
Register Transfer Level Design Library for the Iowa Logic Simulator

                             Version

                                by
                         Douglas W. Jones
                        University of Iowa
                               1998

                        jones@cs.uiowa.edu

This directory contains a small assortment of useful register-transfer
level components, described in the Iowa Logic Specification Language.
This collection is currently incomplete and should be considered only
as a demo of the possibility of building a larger library:

The files here are:

   README    -- this text

   comp      -- a comparator; compares two words for equality
   mux2      -- a 2-word multiplexor
   ram       -- a generic RAM
   reg       -- a generic one-word register

Copyright notice:  The author explicitly grants unlimited rights to copy,
modify, sell, or otherwise distribute copies of these files, with no
strings attached!
xxxqzzqxxx
cat > comp <<\xxxqzzqxxx
circuit comp( range word, time speed ); -- designed by D. W. Jones
  -- parts C: comp( 1..4, s ) makes C as 4 bit by 2 way comparator
  -- C.out equals 1 only when C.inA and C.inB are equal 4-bit words.
  -- the propagation delay through C is s.

time	W = speed / 7.0;
	  -- there are 3 levels of wires
time	G = 2 * W;
	  -- there are 2 levels of gates
	  -- note that 3(W)+2(G) = 3(W)+2(2W) = 3(W)+4(W) = 7W

inputs
	inA(word),
	inB(word),

outputs
	out;

parts
	compbit(word): xor(G);
	combine: nor(size(word),G);

wires
	{ data paths }
	for i in word do
	    inA(i) to(W) compbit(i).in(1);
	    inB(i) to(W) compbit(i).in(2);
	    compbit(i).out to(W) combine.in((i - first(word)) + 1);
	endfor;
	combine.out to(W) out;
end.
xxxqzzqxxx
cat > mux2 <<\xxxqzzqxxx
circuit mux2( range word, time speed ); -- designed by D. W. Jones
  -- parts M: mux2( 1..4, s ) makes M as a 2 input by 4 bit mux
  -- M.in0 is selected when M.select is zero.
  -- the word size is 8 bits with bits numbered 0..7
  -- the total propagation delay for M is s.

time	W = speed / 10.0;
	  -- there are 4 levels of wires
time	G = 2 * W;
	  -- there are 3 levels of gates
	  -- note that 4(W)+3(G) = 4(W)+3(2W) = 4(W)+6(W) = 10W

inputs
	in0(word),
	in1(word),
	select;

outputs
	out(word);

parts
	inv: not(G);
	
	sel0(word): and(2,G);
	sel1(word): and(2,G);
	mix(word): or(2,G);

wires
	{ data paths }
	for i in word do
	    in0(i) to(W) sel0(i).in(1);
	    in1(i) to(W) sel1(i).in(1);
	    sel0(i).out to(W) mix(i).in(1);
	    sel1(i).out to(W) mix(i).in(2);
	    mix(i).out to(W) out(i);
	endfor;

	{ control }
	select to inv.in;
	for i in word do
	    inv.out to(W) sel0(i).in(2);
	    select to(W) sel1(i).in(2);
	endfor;
end.
xxxqzzqxxx
cat > ram <<\xxxqzzqxxx
circuit ram( range addrbit; range databit; time speed );
  -- parts M: ram( 0..3, 0..7, s ) makes M as a 16 word x 8 bit memory.
  -- 16 words because the address has 4 bits bits (numbered 0..3)
  -- the word size is 8 bits with bits numbered 0..7
  -- M is positive pulse triggered.
  -- the access time for M is s.

range   addrange = 0 .. 2**size(addrbit) - 1;
	  -- the range of legal memory addresses
integer	membits = size(addrange) * size(databit);
	  -- the total number of bits in the RAM
range	bitrange = first(databit) .. (membits + first(databit) - 1);
	  -- the index range for the array of bits in the RAM

time    W = speed / 19;
	  -- wire delay (there are 7 levels of wires)
time    G = 2 * W;
	  -- gate delay (there are 6 levels of gates)
	  -- note that 6(2W)+7(W) = 12W+7W = 19W

inputs
	addr(addrbit),  -- the address
	data(databit),  -- the data input
	strobe;		-- positive pulse triggered

outputs
	out(databit);	-- the contents of the addressed word

parts
	inv(addrbit): not(G);
	  -- each address input must be inverted to decode addresses
	dec(addrange): and(size(addrbit),G);
	  -- gates used for row decoding
	rowstrobe(addrange): and(2,G);
	  -- gates to enable strobe for rows
	bits(bitrange): latch(G);
	  -- the memory array itself
	bitgate(bitrange): and(2,G);
	  -- output enable for each cell
	outdriver(databit): or(size(addrange),G);
	  -- output driver for each data bit

wires
	{ invert the inputs }
	for i in addrbit do
	    addr(i) to(W) inv(i).in;
	endfor;

	{ wire each row }
	for j in addrange do

	    { wire each input of the row decoding gate }
	    for i in 1 .. size(addrbit) do
		if ( (j/2**(i-1)) mod 2 ) = 0 then
		    inv(i+first(addrange)-1).out to(W) dec(j).in(i);
		else
		    addr(i+first(addrange)-1) to(W) dec(j).in(i);
		endif;
	    endfor;

	    { strobe the row }
	    strobe to rowstrobe(j).in(1);
	    dec(j).out to(W) rowstrobe(j).in(2);
	    
	    for i in databit do
		{ wire row j column i }
		{ note, row 0 goes first(databit)..last(databit) }
		{ row n adjust subscript by n*size(databit) }

		rowstrobe(j).out to(W)
		    bits(i + j*size(databit)).control;
		data(i) to(W)
		    bits(i + j*size(databit)).data;
		bits(i + j*size(databit)).out to(W)
		    bitgate(i + j*size(databit)).in(1);
		dec(j).out to(W)
		    bitgate(i + j*size(databit)).in(2);
		bitgate(i + j*size(databit)).out to(W)
		    outdriver(i).in(j - first(databit) + 1);
	    endfor;
	endfor;

	{ wire each output }
	for i in databit do
	    outdriver(i).out to(W) out(i);
	endfor;
end.
xxxqzzqxxx
cat > reg <<\xxxqzzqxxx
circuit reg( range word, time speed ); -- designed by D. W. Jones
  -- parts R: reg( 1..4, s ) makes R as a 4 bit register
  -- R.in is copied to R.out on the positive edge of R.strobe
  -- the total propagation delay for R is s.

time	W = speed / 10.0;
	  -- there are 4 levels of wires
time	G = 2 * W;
	  -- there are 3 levels of gates
	  -- note that 4(W)+3(G) = 4(W)+3(2W) = 4(W)+6(W) = 10W

inputs
	in(word),
	strobe;

outputs
	out(word);

parts
	inv: not(G);
	
	master(word): latch(G);
	slave(word): latch(G);

wires
	{ data paths }
	for i in word do
	    in(i) to(W) master(i).data;
	    master(i).out to(W) slave(i).data;
	    slave(i).out to(W) out(i);
	endfor;

	{ control }
	strobe to inv.in;
	for i in word do
	    inv.out to(W) master(i).control;
	    strobe to(W) slave(i).control;
	endfor;
end.
xxxqzzqxxx
chmod go+r *
cd ..

echo  Done.  Note that, as created, the directory rtl
echo  and all files in it are publically readable.