LIS R4,0 3 2 1 0
TESTR R3
BZS L2 0 _E3 _F0 _00 _D4
L1:
ADDSI R4,2 4 _C2 _14 _03 _02
ADDSI R3,-1
BZR L1 8 _FD _0A _CF _13
L2:
a) Hand assemble this code into the blanks above. Your result should be a sequence of 32-bit words expressed in hexadecimal. You may want to work out the sequence of bytes or halfwords first in the large blank space. (3 points)
Here is what we get if we use a computer to assemble it:
+00000000: D4 00 3 LIS R4,0 +00000002: F0 E3 4 TESTR R3 +00000004: 02 03 5 BZS L2 6 L1: +00000006: 14 C2 7 ADDSI R4,2 +00000008: 13 CF 8 ADDSI R3,-1 +0000000A: 0A FD 9 BZR L1 10 L2:1/10 had perfect scores, 3/10 gave answers that were essentially nonsense. Among those earning partial credit, most made varying numbers of small clerical errors but 1/10 consistently swapped the order of the bytes in each halfword.
b) Take the time to figure out what the code accomplishes and then give a sequence of two instructions that together have the same effect on R3 and R4: (1 point)
__MOVESL__R4,R3,1__
__LIS_____R3,0_____
1/10 did well, 2/5 earned no credit, giving essentially nonsensical descriptions of what the above code does. Among those earning partial credit, many focused on the first instruction and forgot to zero out R3.
11 10 09 08 07 06 05 04 03 02 01 00 s exp mant
- s -- the sign of the number.
- exp -- the biased exponent, similar to the IEEE system.
- 0000 -- used for non-normalized numbers.
- 1111 -- not a number or infinity.
- 0111 -- the encoding of zero in this biased number system.
- mant -- the mantissa, with a hidden bit as in the IEEE system.
- The point is between the hidden bit and bit 6.
Convert each of the following decimal numbers to binary in this format: (1 point each)
a) 1.750 = _0 _0 _1 _1 _1 _1 _1 _0 _0 _0 _0 _0
b) 17.50 = _0 _1 _0 _1 _1 _0 _0 _0 _1 _1 _0 _0
c) 175.0 = _0 _1 _1 _1 _0 _0 _1 _0 _1 _1 _1 _1
1/4 did perfect work. Another 1/4 got part a correct and had difficulty with the larger numbers. 2/5 had trouble with the larger exponents, and 1/2 had difficulty with the larger mantissas.
MACRO LIL =dst,=const
IF TYP(const)=0
IF (const > 32767) ! (const < -32768)
LIS dst, (const >> 16)
ORIS dst, (const >> 8) & #FF
ORIS dst, (const ) & #FF
ELSEIF (const > 127) ! (const < -128)
LIS dst, (const > 8)
ORIS dst, (const ) & #FF
ELSE
LIS dst, const
ENDIF
ELSE
LOAD dst,qCONSTPOOLq
qLCSAVEq=.
.=qCONSTPOOLq
W const
qCONSTPOOLq=.
.=qLCSAVEq
ENDIF
ENDMAC
a) How does this macro expand LIL R3,#123? Please simplify the expressions in the operands. (1 point)
____LIS_____R3,#01________________ ____ORIS____R3,#23________________ __________________________________ __________________________________
1/10 did well here, 1/5 earned no credit. Among those earning partial credit, 1/5 gave answers without simplifying the expressions; worse, 1/10 merely stated that an LIS/ORIS sequence would be used, without any statement of operands. 1/10 gave the wrong simplification, stating that the constant #123 would br broken into #12 followed by #3.
b) When this macro expands LIL R1,PUTCHAR to LOAD R1,qCONSTPOOLq, what does it put at the location pointed to by qCONSTPOOLq? (1 point)
____W_______PUTCHAR_______________ __________________________________ __________________________________ __________________________________
1/10 did well, 2/5 earned no credit. Among those earning partial credit, 1/5 stated that PUTCHAR was put into that memory location, without stating whether it was a byte, halfword or word. Among those earning no credit, 1/5 gave strange answers involving the program counter or the location counter.
c) When this macro expands LIL R1,PUTCHAR to LOAD R1,qCONSTPOOLq, where should qCONSTPOOLq point? (1 point)
____Just_after_the_end____________ ____of_the_code___________________ __________________________________ __________________________________
1/10 gave essentially this answer, while 1/5 read this as a duplicate of part b) and said that qCONSTPOOLq points to a pointer to PUTCHAR, for partial credit. 3/5 earned no credit; wrong answers included qLCSAVEq, the program counter, the activation record, or the subroutine.
LOADS R3,R4
A problem: If R4 might not be aligned and we want to load the word it points to, that is, any four consecutive bytes, we can use the following code, using R1 as a scratch register in order to avoid messing with R4. Fill in the blanks to complete it: (3 points)
LOADS R3,R4
BTRUNC R4,2
BR DONE
BR L1
BR L2
L3:
_LOAD_ _R1,R4,1__
SL R1,8
SRU R1,8
SL R3,12
ADDSL R3,R1,12
BR DONE
L2:
LOAD R1,R4,2
_TRUNC _R1,16____
ADDSL R3,R1,16
BR DONE
L1:
LOAD R1,R4,3
TRUNC R1,8
_ADDSL _R3,R1,8__
BR DONE
DONE:
1/25 gave perfect answers, 3/10 gave excellent answers to the first and third blank. On the second blank 1/5 earned partial credit with sensible ideas about things like TRUNC or EXTH instructions. On the third blank, 3/10 earned partial credit with incorrect shift counts, incorrect register usage, or other errors. Only 1/10 earned no credit at all. Among the common errors for any of the blanks that earned no credit at all were ALIGN directives, strange shifts that discarded all of the significant bits from a register, and STORE instructions.
Apology: In point of fact, the code given was nonsense. Nobody pointed this out; The errors in the code have no effect on the first blank, but the middle blank and final blanks were entirely wrong. Those earning full credit either inferred the erronious pattern from which I constructed the code, or without comment, they tried something that was a correction to my error without noting my error. The correct code is left as an excersise; it is no more complex than the code given.
a) Assume that inputs d and c are held at unknown but constant values, and that input u briefly goes to zero. What happens? The answer may depend on several unknowns, so you may need to consider several cases before you draw a conclusion. (1 point)
_Q_goes_low;_if_r_is_low_both_outputs_stay_low___
1/25 gave perfect answers, 3/10 only said Q goes low, without further clarificaiton.
b) Assume that inputs d and c are held at unknown but constant values, and that input v briefly goes to one. What happens? (1 point)
_Q_bar-bar_goes high;_if_u_is_hight_both_outputs_stay high
Only 1/50 gave a perfect answer, and 1/5 earned partial credit. Parts a) and b) were symmetrical, so it is puzzling that a number of students gave different quality answers to the two parts.
c) Assume that input u is held high and v is held low, and that data is presented at input d. What action on the clock input c will transfer d to Q. (1.0 point)
__a_trailing_edge________________________________
3/10 gave excellent answers, and another 3/10 earned partial credit for either answering that c=0 allowed the output to change or that it was some kind of edge triggered flipflop.
___None_________________________________________ ________________________________________________ ________________________________________________ ________________________________________________
1/10 earned full credit. Another 1/10 gave narratives of various lengths from which the correct conclusion could be drawn, but did not draw a conclusion. A few said that this code sets the most significant bit of R3 to zero; it does not, but the reason lies in the fine print of the manual, so this answer suffered only a small penalty. Over 1/5 concluded that this code multiplies by 1/2, 3/2, or 3; these answers earned partial credit because they involve reasonable misreadings of the relationship between left and right shifts on the Hawk. Over 1/10, however, concluded that this code divides by 3. This is unreasonable, and any student who was curious enough to explore the readings for the course should have noticed that division by 3 is far harder than this.
MOVE R1,R3
SRU R3,1
ADDSRU R3,R1,1
A Question
This code takes the unsigned value in R3 and multiplies it
by what?
(1.0 point)
____Times_3/4___________________________________ ________________________________________________ ________________________________________________ ________________________________________________
1/5 gave excellent answers. 3/10 earned partial credit for answers like 5/4 or 5/16 that, at least, involve the right number of partial products and small shifts.
ADD R5,R3,R4
ADDC R5,R0
A Problem: Suppose the double-registers R3-R4 and R5-R6 contain 64-bit one's complement numbers, with the least significant halves in the lower-numbered registers. Give code to add the two numbers, leaving the result in R3-R4. (2 points)
________ADD______R3,R3,R5_______________________ ________ADDC_____R4,R6_______;_a________________ ________ADDC_____R3,R0__________________________ ________ADDC_____R4,R0_______;_b________________
1/50 gave a perfect answer. Among those earning partial credit, 3/10 of the class omitted the line marked b, and 1/5 of the class split the line marked a into an ADDC followed by an ADD. 1/10 left this problem blank, and 1/10 gave strange answers that earned no credit.
Splitting the line marked a into ADDC R4,R0 / ADD R4,R4,R6 does not work because the ADD discards any carry out of the ADDC, while the combined instruction preserves everything.
Omitting the line marked b ignores the possibility that the second ADDC might produce a carry out. This is a subtle point, so the penalty for omitting this instruction was small.