Assignment 12, Solutions

Notice: This assignment is entirely prepratory for the final programming project.

1. Background: The Hawk has several undefined instructions. Here, we define undefined entirely in terms of the opcode field (or fields) and not in terms of values of other fields. For example, in addition to undefined instructions, there are instructions that are not defined when some register field equals zero -- ignore these!

   a) Identify all of the undefined instrucitons in the Hawk instruction set. For each, give the opcode in hexadecimal, with X replacing fields of the instruction halfward that are not part of the opcode. (0.5 points)

   The bits of the two consecutive bytes, quoting directly from Appendix B.1.

   1111XXXX 0001XXXX Section B.1.2
   1111XXXX 0000XXXX Section B.1.2
   0001XXXX 1000XXXX Section B.1.9
   0001XXXX 0100XXXX Section B.1.10
   00001000 XXXXXXXX Section B.1.11

   But when the consecuitve bytes are assembled into words, the byte order is reversed, so as halfwords, the values we want are:

   0001XXXX1111XXXX
   0000XXXX1111XXXX
   1000XXXX0001XXXX
   0100XXXX0001XXXX
   XXXXXXXX00001000

   b) For each of the above, classify it as one where the CPU architecture would encourage defining it as a short instruction (16 bits), or a long instruction (32 bits), and whether the fields you marked with X in part a should best be interpreted as identifying registers or something else. (0.5 points)

   0001XXXX1111XXXX
   0000XXXX1111XXXX
   The above two are from B.1.2, Where the memory reference format instructions such as LOAD and STORE are given. All of these are 32 bit instructinos where the fields marked XXXX above are used to designate registers.

   1000XXXX0001XXXX
   The above is from B.1.9, where two-register instructions such as AND and SUBB are given. These are 16-bit instructinos where the fields marked XXXX above are used to designate registers.

   0100XXXX0001XXXX
   The above is from B.1.10, a collection of special instructions. These are 16-bit instructions where the XXXX field in the first (least significant) byte specifies a CPU register, but the other XXXX field typically specifies something different, a coprocessor register, a special register or an "adjustment".

   XXXXXXXX00001000
   The above is from B.1.11, where all the branch instructions are. These are 16-bit instructions where the XXXXXXXX field making up the entire second (high) byte of the instruction is a branch displacement.

2. Background: Assume you are writing code within a trap handler, where the registers are saved the trap save area pointed to by R2, as in the trap framework defined in Chapter 13 of the hawk manual. Assume that the entire CPU state has been saved.

   a) Write a code fragment that loads the instruction pointed to by the saved program counter into R3. This should only take 2 to 4 instructions, but note, you have a halfword pointer, so one of these instrucitons will need to be EXTH. (0.5 points)

           LOAD    R4,R2,svPC
           LOADS   R3,R4
           EXTH    R3,R3,R4
   

   b) Write a code fragment that assumes that an instruction halfword has been loaded into R3 and extracts bits 8 to 11 (the destination register field) into the low 4 bits of R4. This should only take 2 to 4 instructions. (0.5 points)

   WAIT! The destination register field is the low bits of the first byte of the instruciton, and the first byte is the least significant byte. Therefore the above question must contain an error! One of the two solutions that follow would make sense in the context of this error:

   ; assume it intended the destination register
           MOVE    R4,R3
           TRUNC   R4,4
   
   ; assume it intended the register specifiec by bits 8 to 11
           MOVE    R4,R3
           SR      R4,8
           TRUNC   R4,4
   

   c) Write a code fragment that assumes that an instruction halfword has been loaded into R3 and branches to ISADDC if the opcode is the opcode for the ADDC instruction. You may use R5 as a temporary register. This should only take 2 to 4 instructions. (Note that, since the ADDC instruction is not undefined, the trap handler would never see this instruction; ADDC is used here to set an example that does not conflict with problem 1.) (0.5 points)

           LIL     R5,#F0F0
           AND     R5,R3
           CMPI    R5,#7010
           BEQ     ISADDC
   

   d) Write a code fragment that assumes that the low 4 bits of R4 hold a register number extracted from the instruction that caused the trap and loads R5 with the contents of the memory location pointed to by the value the user had in that register at the time of the trap. This should only take 2 to 4 instructions.

           LEA     R5,R2,svPC      ; note that PC is R0
           ADDSL   R4,R5,2
           LOADS   R5,R4