clock | o-- _______________ | | |--------> 2 16 bit addresses to memory | | Instr Fetch |<-------- 2 16 bit words from memory | |_______________| o-- _|_SRC_|_DST_|_ | | |--------> 16 bit address to memory | | Op Fetch |<-------- 16 bit word from memory | |_______________| o-- _|_OP__|_DST_|_ | | |--------> 16 bit address to memory | | Op Store |--------> 16 bit word to memory | |_______________| -----> 1 bit, write | | ---------------------Note that every pipeline stage always reads or writes on every clock cycle, and that the write line (a copy of the clock signal) is included here only because it will need to be modified in completing this assignment.
NOTE: This is not the pipeline scheme mentioned in the previous assignment. It is the scheme used in offering of this course and in the published version of the ultimate RISC paper.
Part A: Show the interlock logic you would use to delay the operand fetch stage on this pipe in case the previous instruction in sequence involved a store to that location.
Ignore the possibility of result forwarding, and ignore self modifying code, do not show internal details of any pipeline stages, and ignore the fact that things like the ALU are out on the bus.
Part B: Show the result forwarding logic you would use to forward the data being written to memory to the operand fetch stage in order to eliminate the need for an interlock.
Again, do not show internal details of any pipeline stages, ignore the fact that some items on the bus are not memory, etc.
Part C: The ALU for the Ultimate Risc is out on the bus! As a result, a read from location A may not return the value most recently written to location A. For example, if A is the ALU address used for "add to accumulator" on write and "return sign of accumulator" on read.
Knowing this, comment on the desirability of your solutions outlined in parts A and B, assuming that only one or the other was allowed.
Part D: You may use both result forwarding and interlocks! That is, your logic for part A is to be combined with your logic for part B, with added logic used to decide which subsystem, forwarding or interlocks, is to be active. Describe the logic you would use for this decision! The outputs should be two booleans, forward, which is true only when result forwarding should be used, and interlock, which is true only when a bubble should be injected.