Homework 6

22C:122, Fall 1998

Due Monday Oct 5, 1998, in class

1. Consider the Pipelined Ultimate RISC with the following version of the result forwarding logic discussed in class:

   	repeat the following assignments in parallel
   
              if not (dst' = FFFF16)
                then m[dst'] = tmp
   
              tmp = (if src = dst' then tmp else m[src])
              dst' = dst
   
              src = m[pc]
              dst = m[pc + 1]
   	   pc = (if dst = FFFF16 then m[src] else pc + 2)
   
   	forever
   

   This result forwarding logic actually eliminates only some operand delay slots. It does, for example, eliminate the delay slot in:

           MOVE X,Y
           MOVE Y,Z  ; here, Z gets X, as hopes!
   

   In solving the following problmes, assume that the RAM subsystem does not respond to addresses F000₁₆ and up. This range of 4K addresses is reserved for the CPU and for I/O device interface registers. Explain, in each case, why this logic does not eliminate delay slots in the following code fragments:

        a: MOVE X,sub
           MOVE ccN,Y
   
        b: MOVE X,sub
           MOVE acc,Y
   
        c: MOVE X,FFF816
           MOVE FFF816,Y
   
        d: MOVE X,(d+2)
           MOVE .-.,Y
   
        e: MOVE X,Y
           MOVE Y,pc
   

2. Draw a register transfer diagram for the pseudocode description of the CPU given at the start of problem 1. This should implement the logic exactly as shown, without correcting any of the faults illustrated by parts a through e of problem 1.

3. Modify the register transfer logic, either in pictoral form or in pseudocode form, so that the problems illustrated by parts a, b and c are eliminated. (Don't worry about self modifying code or multistep moves into the PC.

4. Note that the above logic eliminates one branch delay slot, but it still has one branch delay slot. Can you add a stall (introducing a bubble) so that the machine has no branch delay slots visible to the programmer?