Examples
Part of
the homework for CS:2820, Fall 2017
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Note, the first posting of these results was based on defective code I wrote. The spirit of the examples was correct, but the details of the timing were wrong.
The solution to MP4 distributed to the class contains an interesting mistake. I had intended to make the gates have no "low pass filter" characteristic. That is, rapid changes to the input of a gate would lead to rapid changes to the gate's output. Instead, my solution is partly a low-pass filter. The following circuit can be used to illustrate this:
gate A const 1.0 gate B not 1.0 gate C not 10.0 wire A true B in 1.0 wire B out C in 1.0
Here is the output you get from my solution to MP4 with this data
At 1.0 gate A const 1.0 true changes to true At 1.0 gate B not 1.0 out changes to true At 3.0 gate B not 1.0 out changes to false At 10.0 gate C not 10.0 out changes to true At 12.0 gate C not 10.0 out changes to true At 14.0 gate C not 10.0 out changes to true
Here is the output you get from my solution to MP5 with the same data
At 1.0 gate A const 1.0 true changes to true At 1.0 gate B not 1.0 out changes to true At 3.0231237 gate B not 1.0 out changes to false At 10.0 gate C not 10.0 out changes to true
Note: I didn't add any randomness to the timing of output changes on const gates, nor to the timing of the initial output change on not gates.
Note: Changing the random number seed will mess with the details of the timing. As a result, attempting to exactly duplicate these results is not wise.
In my code, this partial filtering out of short pulses happens similarly in all logic gates, not just the not gates demonstrated above.
gate A not 9.0 gate B not 9.0 wire A out B in 1.0 wire B out A in 1.0
Running this under MP4 gives this:
At 9.0 gate A not 9.0 out changes to true At 9.0 gate B not 9.0 out changes to true At 19.0 gate B not 9.0 out changes to false At 19.0 gate A not 9.0 out changes to false At 29.0 gate A not 9.0 out changes to true At 29.0 gate B not 9.0 out changes to true At 39.0 gate B not 9.0 out changes to false At 39.0 gate A not 9.0 out changes to false ...
And so on, forever and ever. Running it under MP5 with both low-pass filter behavior and randomness, it comes to a stop after only a few oscillations:
At 9.0 gate A not 9.0 out changes to true At 9.0 gate B not 9.0 out changes to true At 18.571909 gate A not 9.0 out changes to false At 19.208113 gate B not 9.0 out changes to false At 28.780622 gate B not 9.0 out changes to true At 28.940868 gate A not 9.0 out changes to true At 38.605614 gate B not 9.0 out changes to false At 39.164497 gate A not 9.0 out changes to false At 48.338852 gate A not 9.0 out changes to true At 49.15678 gate B not 9.0 out changes to true At 58.327072 gate B not 9.0 out changes to false
Now, look what happens if we shorten the delays on the wires relative to the gates:
gate A not 9.5 gate B not 9.5 wire A out B in 0.5 wire B out A in 0.5
The output from my solution to MP4 still goes on with the same infinite sequence, with the timings shifted a bit but the same period:
At 9.5 gate A not 9.5 out changes to true At 9.5 gate B not 9.5 out changes to true At 19.5 gate B not 9.5 out changes to false At 19.5 gate A not 9.5 out changes to false At 29.5 gate A not 9.5 out changes to true At 29.5 gate B not 9.5 out changes to true ...
But under MP5, this circuit takes a settles down almost instantly:
At 9.5 gate A not 9.5 out changes to true At 9.5 gate B not 9.5 out changes to true At 19.048126 gate A not 9.5 out changes to false
If you continue to lengthen the gate delay (which has both the the random component and sets the the low-pass filtering rate) relative to the wire delays, the result will be less and less likely to oscillate at all, while if you shorten the gate delay relative to the wire delay, it will oscillate for longer and longer, but if there is any random component to the gate delay and if the gates behave as low-pass filters, it will always settle down eventually.
Here's something big
gate A const 1.0 gate B not 1.0 wire A true B in 1.0 -- B out will have a true pulse from time 1 to time 3 gate C not 0.001 wire B out C in 0.001 -- C out will have a false pulse from just after time 1 to time 3 -- applying a true pulse to D in2 sets the outputs to false -- applying a false pulse to E in2 sets the outputs to true gate D or 1.0 gate E and 1.0 wire D out E in1 0.2 wire E out D in1 0.2 -- so now, try to set and reset D and E simultaneously wire B out D in2 1.000 wire C out E in2 0.998
This gives the following output under my solution to MP5:
At 0.001 gate C not 0.001 out changes to true At 1.0 gate A const 1.0 true changes to true At 1.0 gate B not 1.0 out changes to true At 1.0020231 gate C not 0.001 out changes to false At 2.9524345 gate D or 1.0 out changes to true At 3.0231903 gate B not 1.0 out changes to false At 3.0251606 gate C not 0.001 out changes to true At 4.98594 gate D or 1.0 out changes to false At 5.0658126 gate E and 1.0 out changes to true At 6.156299 gate E and 1.0 out changes to false At 6.2649546 gate D or 1.0 out changes to true At 7.35499 gate D or 1.0 out changes to false At 7.514346 gate E and 1.0 out changes to true At 8.536442 gate E and 1.0 out changes to false At 8.719635 gate D or 1.0 out changes to true At 9.751406 gate D or 1.0 out changes to false
It stops, after a while. The and and or gates D and E are the gates in the feedback path that oscillate here, while the other gates are set up to trigger the oscillation. Adjusting the relative timing of the gates and wires in this feedback path changes how long it oscillates.
Note again, use a different random number seed, and you will get different results, both in terms of the exact timings and the number of cycles before the oscillator settles down into one or the other stable state.