Machine Problem 5, due Nov. 13

Background:

The solution to MP4 distributed to the class contains an interesting mistake. I had intended to make the gates have no "low pass filter" characteristic. That is, rapid changes to the input of a gate would lead to rapid changes to the gate's output. Instead, my solution is partly a low-pass filter. The following circuit can be used to illustrate this:

gate A const 1.0
gate B not 1.0
gate C not 10.0
wire A false B in 1.0
wire B out C in 1.0

Here is the output I expected:

At 1.0 gate A const 1.0 true  changes to true
At 1.0 gate B not 1.0 out  changes to true
At 10.0 gate C not 10.0 out  changes to true
At 12.0 gate C not 10.0 out  changes to false

Here is the output the program actually generates:

At 1.0 gate A const 1.0 true  changes to true
At 1.0 gate B not 1.0 out  changes to true
At 10.0 gate C not 10.0 out  changes to false
At 12.0 gate C not 10.0 out  changes to false

That is, output of gate C is initially false, and the simulator announced that it change to false and then changed to false again. What has happened is that any changes to the output of a gate that are then reversed within the delay of that gate are incompletely cancelled. Gate C has a delay of 10.0 and the output pulse is of length 2.0, so it did not make it through. However, the events marking the start and end of that pulse did, producing announcements of changes from false to false.

In my code, this partial filtering out of short pulses happens similarly in all logic gates, not just the not gates demonstrated above.

Part 1

The fact is, we want this low-pass filter behavior, but without the spurious events. Here is the output we really want from the above example:

At 1.0 gate A const 1.0 true  changes to true
At 1.0 gate B not 1.0 out  changes to true

To get this output, you will have to study the code, underatand why it works the way it does, and then fix it. The behavior in question is entirely determined by the simulation methods in class LogicGate and associated subclasses in my code. You should do the repair so that is is equally applicable to all logic gates. That is, short pulses passing through an and or or gate should also be completely filtered out.

Part 2

This low-pass filter behavior really matters in this circuit:

gate A not 9.0
gate B not 9.0
wire A out B in 1.0
wire B out A in 1.0

In the current simulator, this circuit oscillates forever between true and false, with a period of 20.0. If you built this circuit with real hardware, however, it would eventually fall into one of two stable states. Eventually, gate A would have a true output or it would have a false output, with gate B having the opposite.

This can only happen if there is a small random variation in the delay of each gate. Homework 8 problem 4 dealt with this. Implement this, being sure to make your PRNG.randomFloat() code 100% compatible with the specificaitons in that assignment.

Part 3

Split your solution into multiple source files, so that your code for class Gate and all of its subclasses is contained in file Gate.java.

Submit

Following the usual submission guidelines, including requirements for header comments, submit only your code for Gate.java. We will compile your code along with our code for all of the other classes required when we test it.

Our version of class PRNG conforms to the interface documented in Homework 8, and all of our other classes will be exactly the code from the solution distributed to MP4.

One additional requirement we are imposing: Minimize your changes. Do not make gratuitous changes to indenting, spacing, comments or the order of elements of my code. The code you do add should be properly commented, of course, and you must credit authorship properly, as usual.