Assignment 8, due Oct 20

Assignments are to be turned in on paper. On every assignment, write your name, course and section number at the top. Write your name as it appears in your university records! Use the section number for which you are registered! We will not do detective work to figure out who did what. Work must be legible. Homework is due on paper in discussion section, usually at the start except when the assignment indicates that time to work on the assignment will be provided in class. Exceptions will be made only by advance arrangement with your TA (excepting "acts of God" outside your control). Never push homework under someone's door!

1. Background: In the posted solution to Machine Problem 3, a flat class hierarchy is used, where class Gate has, as equal subclasses, classes AndGate, OrGate, NotGate and ConstGate. The result has considerable code duplication.

   Consider this alternative class hierarchy:

                                Gate
                               /    \
                      LogicGate      ConstGate
                     /         \
           TwoOutGate           NotGate
          /          \
   AndGate            OrGate
   

   a) Look at each of the fields and methods declared in classes AndGate, OrGate, NotGate and ConstGate, and identify each field or method that should be moved into class TwoOutGate in order to minimize code duplication. For each method moved, identify the class or classes it comes from and identify any challenges posed by moving the code. (0.5 points)

   b) Look at each of the fields and methods declared in classes AndGate, OrGate, NotGate and ConstGate, and identify each field or method that should be moved into class LogicGate in order to minimize code duplication. Use the rules for stating your answer given above. (0.5 points)

2. Background: Now, consider the problem of const gates in the context of the posted solution to MP3. When the power comes on, which is to say, when the simulation starts, all the wires and all of the outputs of all of the gates are at logical false. After delay, the true output of each const gate goes from false to true.

   Assume that class ConstGate has a method outputChangeEvent(t) that is used only for the change described above, where the parameter t indicates the time at which the change occurs.

   a) Where in the code for class ConstGate should the code go that schedules outputChangeEvent? In the context of the posted solution to Machine Problem 3, there are just two reasonable answers. (0.5 points)

   b) Write the code that schedules outputChangeEvent using the simulation framework at the end of the notes for Oct. 10. This code should be written so that it can be "pasted" into the location you give in part a) of this problem. (0.5 points)

3. Background: The code distributed for ScanSupport in the posted solution to MP3 includes nextFloat but not nextInt. Our highway network example really needs nextInt. Most of the logic for nextInt can be borrowed trivially from nextFloat: The pattern for integers much simpler than the one for floating point, and you call Integer.parseInt instead of Float.parseFloat. can be stolen from nextFloat

   A problem: There is exactly one part of nextFloat that has no usable analog that would work in the context nextInt. (It involves a feature of class Float that has no analog in the context of class Integer.) (0.5 points)

4. Background: One possible consequence of an input change event on a logic gate is an output change. In a simple simulator, this occurs at a constant delay after the input change event, so the code in the input-change event routine would look something like this:

   schedule( time + delay, ... );
   

   Assum you have written class PRNG discussed in the notes for Lecture 15, with a method randomFloat(f) that returns a value from 0.0 to f (some positive floating point scale factor).

   A problem: In a real logic simulator, gate delays are not constant. Rather, they vary slightly and randomly each time a gate's output is changed. Rewrite the above code fragment so that delays vary over approximately a 10% range from 0.95 to 1.05 times the base delay for the gate. (0.5 points)