The Iowa Logic Simulator is an interactive program which allows digital circuit designs to be tested without the need to actually build them. The simulator reads circuit descriptions written in the Iowa Logic Specification Language (defined in Chapter 2); this is a textual language, so any available text editor can be used to create circuit descriptions. The syntax of this language borrows many elements from familiar programming languages, but it is not a procedural language; rather, it describes the parts of a digital system and the pattern of their interconnection.
Given an error-free circuit description, the Iowa Logic Simulator will repeatedly request simulated inputs to the circuit, and it will display the resulting outputs as waveforms on the terminal screen. As such, it emulates a logic analyzer as it would be used in debugging a real digital system. The simulator can reproduce the detailed timing of digital systems because it uses a discrete-event simulation model. These facilities are explained in Chapter 3.
The following circuit will be used as an example to illustrate the use of the logic simulator throughout this manual:
It should be noted that, as of Version 9, the Iowa Logic Simulator is not yet the tool we desire, but it is very powerful. The largest circuit it has been used to simulate (to date) is a central processor with 16 registers (6 bits each), an arithmetic logic unit, and an accumulator, with a microcoded control unit containing a 16 instruction writable microstore; this was a class assignment in 1987. Software we would like includes a preprocessor to allow truth table and equational notation in the input, a graphics editor for logic circuits, and a graphic interface to the simulation routines.