Homework 5 - Midterm

22C:122, Spring 1998

Due Wednesday Apr 1, 1997, in class

1. As background, recall the conventional CISC model for implementing procedure calls in languages of the Algol family:

       Stack
     |///////|
     |_______|<-- SP
     |       |        Calling Seq       Receiving Seq
     | local |           
     | vars  |          push FP          f: push locals
     |_______|          move SP to FP         .
     |__ra___|          push params           .  index locals from FP
     |       |          call f pushes ra      .
     | params|                              return n
     |_______|<-- FP
     |__ofp__|        The return n instruction pops n local vars,
     |       |        pops ra into PC, moves FP to SP, and pops ofp into FP
     | caller|
   

   design a calling sequence for a RISC machine where interrupts must be processed on the same stack as is used for procedure and function calls. Therefore, one of the registers must be used as a stack pointer. Your goal is to eliminate the need for a frame pointer and design the simplest universal calling sequence you can!

   For the RISC machine, assume each instruction requires no more than one memory cycle, assume the call instruction stores the return address in a register, and assume that we do not use a frame pointer!

2. Given your calling sequence, how would you handle interrupts? Assume that the interrupt forces a value into the PC and PSW, and saves the old PC and PSW in dedicated hardware registers (the PCSV and PSWSV registers). Assume you can copy from these to general registers, and that the RTI instruction copies from these back to the PC and PSW. Your answer should consist of instruction level pseudocode for interrupt entry and exit, and your code sequences should allow recursive interrupts, where a higher priority interrupt can interrupt the body of a low priority interrupt service routine..

3. Consider the problem of building a machine that supports non-aligned fetches of 16 bit words from a byte addressable memory. Here is an overview of the structure:

               Memory Data   Alignment
                Register        MUX
                   __           __
                  |  |---------|  |-----------| 
          High    |  |         |  |  \    /   |/
          Byte    |  |         |  |   \  /    |------
                  |__|---------|__|-\  \/  /--|
                   |            |    \  \ /   |  16 bit
                 --           --      \  \    |  data from
                |  __        |  __   / \  \   |  memory
                | |  |---------|  |-/  /\  \--|
          Low   | |  |         |  |   /  \    |------
          Byte  | |  |         |  |  /    \   |\
                | |__|---------|__|-----------| 
                |  |         |  |
    Clock high -   |         |  |   Mux controls are 2 bits each
    Clock low  ----          |  |    00 - output zero
                Highmux -----   |    01 - output lower input
                Lowmux  --------     10 - output upper input
   

   Design a controller for the above alignment network that takes the following signals from the CPU:
   • MLSB - least significant bit of memory address
   • WORD - 1 if this is a word address, 0 if a byte address
   • SECOND - 1 if this is a followup fetch after the first
   Your controller should produce the following outputs:
   • Clock high
   • Clock low
   • High mux
   • Low mux
   • Need more
   The need more signal indicates to the control unit that it should initiate a second memory read cycle to read the second half of a non-aligned word. On the second cycle, the memory address will be incremented by two bytes and SECOND will be set to 1.