Consider the following instruction set for a 32 bit computer with 16 general registers r[0] to r[15] and a program counter PC. In the following, all displacements and constants are sign extended to 32 bits unless noted. There is one conditon code register, cc, set only by the indicated instructions. r[0] is always zero and results assigned to it are discarded. Memory addresses are to the byte, but the least significant two bits are ignored on load and store -- which always load and store word-aligned 32 bit longwords. Instructions are packed in consecutive 16 bit words, and some instructions include a 16 bit extension. Thus, the program counter is always even.
Memory Reference Format _______________________________________________________________ |_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_| | | rd | rx1 | rx2 | const | 0 0 0 0 LOAD r[rd] <- m[const + r[rx1] + r[rx2]] (sets cc) 0 0 0 1 STORE m[const + r[rx1] + r[rx2]] <- r[rd] 0 0 1 0 LEA r[rd] <- const + r[rx1] + r[rx2] 0 0 1 1 JSR pc <- const + r[rx1] + r[rx2]; R[rd] <- oldpc Long Immediate Format _______________________________________________________________ |_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_| | | rd | const | 0 1 0 0 LIL r[rd] <- const Short Immediate Format _______________________________ |_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_| | | rd | const | 0 1 0 1 LIS r[rd] <- const 0 1 1 0 ORIS r[rd] <- (r[rd] << 8) | no_sign_extend(const) 0 1 1 1 Bcc if condition_holds(cc) pc <- pc + const Arithmetic -- all of these set cc! _______________________________ |_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_| | | rd | rs1 | rs2 | 1 0 0 0 ADD r[rd] <- r[rs1] + r[rs2] 1 0 0 1 SUB r[rd] <- r[rs1] - r[rs2] 1 0 1 0 AND r[rd] <- r[rs1] and r[rs2] 1 0 1 1 OR r[rd] <- r[rs1] or r[rs2] 1 1 0 0 XOR r[rd] <- r[rs1] xor r[rs2] 1 1 0 1 EXTB r[rd] <- r[s1] byte-select r[s2] 1 1 1 0 EXTW r[rd] <- r[s1] word-select r[s2]Note that the byte-select operation extracts one byte from the left-hand operand, as selected by the least significant two bits of the right-hand operand. The word-select operation extracts one word as selected by the least significant bit.
Two operand _______________________________ |_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_| | | rd | | rs | 1 1 1 1 0 0 0 0 LOADR r[rd] <- m[r[rs]] (sets cc) 1 1 1 1 0 0 0 1 STORER m[r[rs]] (sets cc) <- r[rd] 1 1 1 1 0 0 1 0 MOVER r[rd] <- r[rs] 1 1 1 1 0 0 1 1 JSRR pc <- r[rs]; R[rd] <- oldpc 1 1 1 1 0 1 0 0 LSL r[rd] <- r[rd] << r[rs] unsigned 1 1 1 1 0 1 0 1 LSR r[rd] <- r[rd] >> r[rs] unsigned 1 1 1 1 0 1 1 0 ASL r[rd] <- r[rd] << r[rs] signed 1 1 1 1 0 1 1 1 ASR r[rd] <- r[rd] >> r[rs] signed 1 1 1 1 1 0 0 0 LSLI r[rd] <- r[rd] << rs unsigned 1 1 1 1 1 0 0 1 LSRI r[rd] <- r[rd] >> rs unsigned 1 1 1 1 1 0 1 0 ASLI r[rd] <- r[rd] << rs signed 1 1 1 1 1 0 1 1 ASRI r[rd] <- r[rd] >> rs signed 1 1 1 1 1 0 0 0 ADDI r[rd] <- r[rd] + rs 1 1 1 1 1 0 0 1 SUBI r[rd] <- r[rd] - rs 1 1 1 1 1 1 1 0 STUFFB r[rd] <- r[rd] byte aligned r[rs] 1 1 1 1 1 1 1 1 STUFFW r[rd] <- r[rd] word aligned r[rs]The byte align instruction truncates the left operand to one byte and then shifts it left 1, 2, 3 or 4 bytes, depending on the least significant two bits of the right operand. The word align instruction truncates the left operand to a 16 bit word then shifts it depending on the least significant bit of the right operand.
Question 1 Give an efficient macro to load a 32 bit constant.
Question 2 Give a macro to branch to an arbitrary absolute address.
Question 3 Present macros for load and store operations on 16 bit word and 8 bit byte operands.
Question 4 Find all the pipeline interlocks required in a natural pipelined implementation of this architecture.
Question 5 What problems would this architecture pose for a superscalar pipelined implementation?
Question 6 This instruction set is missing instructions for housekeeping and interrupt response. There is some room in the instruction set for expansion, but it may not be obvious. List the opcodes that can be used for such applications.
Question 7 Given your solutions to all of the above, plus everything you have learned in this course, present a summary evaluation of this architecture.