Homework 5

22C:122, Spring 1996

Due Monday Mar. 6, 1995

1) What logic needs to be added to the pipelined Ultimate RISC architecture and what conditions must this logic detect to interlock the architecture in order to eliminate operand delay slots and branch delay slots.

2) Consider the design of a memory mapped arithmetic unit for the Ultimate RISC with the following characteristics:

The ALU decodes 9 bits of the operand address, so from the point of view of the programmer, it appears to occupy 512 consecutive memory addresses.
The ALU contains 16 registers and a 4 bit condition code register. Therefore, 4 of the 9 bits of operand address will usually be used to select 1 of 16 registers as either a source or destination operand. This leaves 5 bits to use for operand specification.
The ALU does not perform multiplication or division.
When the ALU is selected as a destination, the operand from the bus may be stored in or combined with any of the 16 registers.
When the ALU is selected as a source, the ALU will either present some function of a selected register to the bus, or it will present a function of the condition codes, as a boolean operand, to the bus.

This design problem is open-ended, and you are invited to use any and all information you can find about operator frequencies to decide what operations and bit assignments to allow for source or destination operands. The only other consideration you might want to apply is that the result should allow for reasonably fast software multiplication.