Homework 9

22C:122/55:132, Spring 2001

Due Friday Mar 30, 2001, in class

Douglas W. Jones
  1. Background: A naive computer architect has suggested that pipelined execution can be usefully applied to any computer. You search the web for a counterexample, and find the Minimal CISC, described at http://homepage.cs.uiowa.edu/~dwjones/arch/cisc/

    Part A: Describe at least two features of this machine that make it extremely difficult to pipeline, explaining, for each, exactly what it is about this feature that stands in the way of pipelined execution.

    Part B: There is at least one feature of this machine that would allow at least a shallow pipelined implementation, and this could lead to a modest performance improvement. Identify the most likely candidate for this feature and explain.

  2. Background: The Ultimate RISC, described at http://homepage.cs.uiowa.edu/~dwjones/arch/risc/ can be pipelined very nicely, with no change to the instruction coding. To do this, we will need to split the memory bus into several busses that can operate in parallel on the same resources. The semantics of the instruction execution unit are described in a brief chunk of pseudocode between Figures 1 and 2 of the paper.

    Part A: Give pseudocode for a pipelined version of this CPU. See the pseudocode for a pipelined VLIW machine in the notes for Lecture 22, as a source for a notation appropriate for this. Assume that the data path to memory (that also provides access to I/O and functional units) offers unlimited parallelism.

    Part B: How many parallel busses providing access to memory did you assume in part A. Which of these are read-only? Which are read-write? Which of them are used for access to RAM but never for access to I/O or functional units?

    Part C: How many operand delay slots does your pipelined IEU introduce (that is, how many instructions must be inserted between an instruction that changes a memory location and a following instruction that inspects that location).

    Part D: How many branch delay slots does your pipelined IEU introduce (that is, how many instructions following a branch instruction will be executed before the instruction that was branched to is fetched.