Homework 4

22C:122/55:132, Spring 2001

Due Friday Feb 9, 2001, in class

Douglas W. Jones

Background: Consider using the approach outlined in Notes on Large Scale System Design (indexed from http://homepage.cs.uiowa.edu/~dwjones/logicsim/) to create a definition of the Minimal Ultimate RISC.
Part A: Give a circuit description for an 1K RAM module, using appropriate register-transfer-leve primitives, as were assumed to be available in the Notes on Large Scale System Design. As with the register example in the notes, your example should assume a global definition word.
You can assume that words are at least 10 bits, but note that version 10 of the Iowa Logic Simulator includes an assert construct, so you can say (just after the circuit heading of any subcircuit):
```
assert first(word) = 0;
assert last(word) > 9;
```
This provides both documentation and a compile-time check of the assumptions you have made.
Part B: Finish the definition of the following register-transfer level component:
```
circuit addressdecode( range word, range subword, integer address);
   -- given A:addressdecode( word, 1..2, 4 )
   -- The values of A.in(1) through A.in(2) are checked against the
   -- cooresponding bits of the constant 4; if they are equal, A.out
   -- is true, else A.out is false.
   assert first(word) = 0;
   assert first(subword) >= 0;
   assert last(subword) <= last(word);
   inputs
      in(word);
   outputs
      out;
```
The address decode function used in the REGISTER example should help, but it checks the entire address, not just the part of the address requested.
Background:: The timing diagram given in Figure 3 of The Ultimate RISC is very complicated, requiring 4 minor clock cycles for each of the 4 phases of the instruction execution cycle. In lecture, a far simpler scheme was discussed, where each phase would have only two subphases.
Part A: Give the simplified timing diagram.
Part B: Why would both timing diagrams work equally well to control the machine?