Homework 3 solved

22C:122/55:132, Spring 2001

Part a: What was the word size of the machine described?
40 bits.

Part b: What was the instruction format?
2 20-bit instructions per 40 bit word
```
 _______________________________________
|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|
|___|___________|_______________________|
| x | ordercode |        address        |
```
The unused bits were not decoded in the order code decoder; only 21 of the 64 possible order codes were assigned meanings (including 2 branches, one branching to the high halfword of the destination address, and one branching to the low halfword of the destination).

Part c: How many registers were available for holding operands?
The accumulator Ac and the (rather anonymous sounding) register R.

Problem: Use the Iowa Logic Specification Language to construct a finite state machine that obeys the given specification.

circuit fsm;

   use register; -- we assume REGISTER(2..0) makes a 3-bit register

   table statetab;
     s(2..0) coin wall  | n(2..0) stop turn  go
     -------------------+-----------------------
      x x x    1   x    | - - -    1    0    0
      0 0 0    0   0    | 0 0 0    0    0    1
      0 0 0    0   1    | 0 0 1    0    1    0
      0 0 1    0   x    | 0 1 0    0    1    0
      0 1 0    0   x    | 0 1 1    0    1    0
      0 1 1    0   0    | 1 0 0    0    0    1
      0 1 1    0   1    | 0 0 1    0    1    0
      1 0 0    0   x    | 1 0 1    0    1    0
      1 0 1    0   0    | 1 0 0    0    0    1
      1 0 1    0   1    | 0 0 1    0    1    0
   end;

   inputs coin, wall, clock;
   outputs stop, turn, go;
   parts
      state: REGISTER(0..2);
      outreg: REGISTER(0..2);
      table: statetab;
   wires
      -- inputs
      coin to table.coin;
      wall to table.wall;

      -- state/next state logic
      state.out to table.s;
      table.n to state.in;

      -- outputs
      table.stop to outreg.in(0);
      outreg.out(0) to stop;
      table.turn to outreg.in(1);
      outreg.out(1) to turn;
      table.go to outreg.in(2);
      outreg.out(2) to go;

      -- clocking
      clock to state.clock, outreg.clock;
   end.

A Problem: Describe how you would go about testing a finite state machine such as the above!
Testing is greatly simplified if the state of the machine is exposed, so I'd begin by adding an extra output to show the machine's current state.
Then, with a copy of the state table next to me, I'd start the machine and repeat the following basic test cycle:
Observe the state the machine is in. If all possible transitions out of that state have not yet been explored, set the inputs to an input that has not yet been tried in that state and clock the circuit. Finally, check the state the machine has moved to and the outputs it produced. This should match the outputs and transition specified in the row of the table you are testing. If it does not, fix the machine. If it does, check off this row as having been tested.
If you find yourself in a state that has been already been exhaustively tested, find a sequence of state transitions from that state to a state that is not yet completely tested and set the inputs so that the machine will move to or closer to that state on the next clock pulse.