Assignment 8, due Mar 26

Always, on every assignment, please write your name legibly as it appears on your University ID and on the class list! All assignments will be due on Fridays at the start of class, and unless there is what insurance companies call "an act of God", the only exceptions to this rule will be by advance arrangement.

1. Consider the example architecture given in the midterm study questions and the subject of much of the midterm exam. Consider this programming problem:

   There is an array of one-word integers A (that starts at address 7FE6₁₆). The size of this array, in words is stored in the variable AS (at address 6A07₁₆). Write code (that begins at address 5000₁₆), where your code computes the sum of the elements of A in register 1 and then jumps to memory address Q (which is 201F₁₆). Parenthetic values are provided for the sake of example, but you are free to substitute symbolic constants into your code.

   Give your result in semi-symbolic form. Here, for example, is a register to register move from R2 to R1, encoded as a load address instruction:

   	load-address R1 R2 000000
   

   And here is code to add R3 to R5:

   	operate R5 R3 add no-skip store
   

   In binary, these would have been:

           1100010010000000
           0001010011+++001
   

   Note that none of the documentation gives the specific encoding used to make the ALU add, so you've got to fake it a bit if you try to give binary!

   One other unspecified detail about the example architecture: Assume that the displacements used for IR.dd are signed 6-bit values from -32 to +31.

2. Cosider designing a coprocessor that can do both integer division and integer multiplication. In the style of the notes for Lecture 21, the division algorithm we will use is:

                 divide:
                    repeat n times -- division loop for an n-bit word
                       -- notation:  a|b means concatenate a and b, n-bits each
                       AC|MQ = AC|MQ << 1;
                       if AC >memory[IR.address]
   		       AC = AC - memory[IR.address]
   		       MQ = MQ or 1  -- the logical or operator
                       endif
   		    -- note: the entire loop body is one register transfer
                    endloop
   

   a) Show a register transfer diagram in the style of the first diagram given in the notes for multiplicaton that shows the data paths needed for division. Note: If you work hard, you can get these data paths to be very close to topologically identical to the data paths shown for multiplication, with the difference only in the shifter, the replacement of an adder with a subtractor, and a few other differences.

   b) Show a register transfer diagram that allows both multiplication and division, with a one-bit control input indicating whether it will function as a multiplier or a divider. Be very careful drawing this for legibility.

   c) How does the bus interface shown in the notes get changed if it is to control this multiply/divide unit. Hint, the change is trivial, you can describe it in a sentence, and remarkably, there is no change at all to the control unit itself.

   d) Give a state diagram for the control unit itself, as a Mealy machine, suitable for use with the original or modified coprocessor from the notes.