Homework 12

22C:122, Fall 1998

Due Monday Nov 30, 1998, in class

1. In class, the following fully associative write-through cache design was presented:

               ______________________________________
   Address bus -----------  -----------------  ------
               ___________||_________________||______
   Data bus    -----------||-------  --------||------
                          ||       ||        ||
         _________     ___||___ ___||___     /\
       -|> Mod N  |___|  Key   |  Data  |   /  \
      | | counter |---|Line        in   |  /____\
      | |_________|   |                 |    ||
      |               |      N-line     |    ||
      |               |   Associative   |    ||
      |               |      Memory     |    ||
      |               |                 |    ||
       ----------o----|>Strobe          |    ||
                 |    |           Data  |    ||
                 |    |__Hit___|___out__|    ||
                 |        |        ||________||
                  --o---  |         ----------
                    |   | |
                    |  _o_|_
                    | | and |
                    | |_____|
                    |    |
                    |    |       ___ 
                    |    o-----o|and|
   Mem Request -----|----|------|___|---------------->
                    |    |      
                    |    |   
   Write -----------o----|--------------------------->
                  ___    |
                 | or|---
   Mem Ack   <---|___|--------------------------------
   

   It was stated in class that this design is incorrect!

   Part A: What is the problem (hint: This design was corrent for the read operation, but each write operation introduces potential problems).

   Part B: Fix the design so that it solves the problem! Hint: You will probably have to change the design of the associative memory to make this change, specifically, as originally given, the associative memory has only one strobe input that changes both halves of the addressed line of the memory. You will need to add a way to change just one of these halves.

2. Use the Iowa Logic Specification Language, http://homepage.cs.uiowa.edu/~dwjones/logicsim/ to fully specify a small cache implemented using the "poor man's" write-through cache architecture based on a conventional RAM. For test purposes, use a 4-bit word, a 200 nanosecond 4-word RAM for the cache, and a 1 microsecond 16 word RAM for the main memory. Note that a small collection of register-transfer level components (rams, registers, multiplexors, etc) is available to simplify your design.