Homework 10

22C:122, Fall 1998

Due Monday Nov 9, 1998, in class

1. The alignment networks presented in class were for input-only and output-only. Show the logic for an input-output alignment network, assuming:
   • 2 bytes per word
   • separate data-in and data-out data paths
   • no support for non-aligned words

2. Part A: Consider the problem of designing a 1 megabit RAM chip with 16 pins. One pin must be dedicated to power, one to ground. How would you use the remainder of the pins?

   Note: this is typical of mid 1980's memory technology. 8 such chips, plus support logic, would be used to make a 1 megabyte RAM for an 8-bit microprocessor, and 32 such chips would be used to make a 4-megabyte 32-bit-word-addressable RAM board for a large UNIX workstation of the era.

   Part B: Given such a chip, outline (at a high level) the supporting logic needed on the 4-megabyte. 32-bit word, word-addressable RAM board, assuming that the data bus includes exactly the following:

   • A tri-state data bus, 32 bits wide.
   • An address but, 22 bits wide, giving the word address.
   • An address-valid signal.
   • A read signal. If asserted, a memory board may write to the data bus.
   • A write signal. If asserted, data may be written to memory.
   • A busy signal, asserted by memory until the operation is complete..
   Note, you may have to use delays (one-shots or short transmission lines) to generate the necessary timing. You can assume that the CPU will assert address-valid an appropriate interval before issuing the read or write signal. For the write operation, address-valid also indicates data-valid.

   Note that there may be 4 memory modules on the bus. Note that the data read from memory is not valid until the memory module ceases indicating busy. The memory must go busy in response to receipt of address-valid if the indicated address refers to it, and it must cease its busy state on completion of the write (initiated by the write signal) or on delivery of data to the bus (initiated by the read signal).

3. Given your memory design above, comment on the applicabilty of interleaving to workstation memory architectures from the mid to late 1980's.