Andrew Reynolds



I am a Research Scientist at the University of Iowa and one of main developers of the Satisfiability Modulo Theories (SMT) solver CVC4. My current research interests include implementing techniques in SMT solvers for unbounded strings and regular expressions, first-order quantified formulas and synthesis conjectures.

Publications

Conference Papers

Workshop Papers

Journal Papers

Technical Reports

Dissertation

Presentations

Competitions

My work in CVC4 has been entered in the following competitions:

Program Committee Experience


Contact Info

E-mail: andrew.j.reynolds@gmail.com